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ABSTRACT
Crosstalk aggressor alignment induces significant interconnect delay variation and needs to be taken into account in a statistical timer. In this paper, we approximate crosstalk aggressor alignment induced interconnect delay variation in a piecewise-quadratic function, and present closed form formulas for statistical interconnect delay calculation with crosstalk aggressor alignment variation. Our proposed method can be easily integrated in a statistical timer, where traditional corner-based timing windows are replaced by probabilistic distributions of crosstalk aggressor alignment, which can be refined by similar delay calculation iterations. Runtime is O(N) for initial delay calculation of N sampling crosstalk aggressor alignments, while pdf propagation and delay updating requires constant time. We compare with SPICE Monte Carlo simulations on Berkeley predictive model 70nm global interconnect structures and 130nm industry design instances. Our experimental results show that crosstalk aggressor alignment oblivious statistical delay calculation could lead to up to 114.65% (71.26%) mismatch of interconnect delay means (standard deviations), while our method gives output signal arrival time means (standard deviations) within 2.09% (3.38%) of SPICE Monte Carlo simulation results.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
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2
|
|
 |
3
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Kanak Agarwal , Dennis Sylvester , David Blaauw , Frank Liu , Sani Nassif , Sarma Vrudhula, Variational delay metrics for interconnect timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
[doi> 10.1145/996566.996675]
|
| |
4
|
Berkeley Predictive Technology Model, http://www-device.eecs.berkeley.edu/~ptm/.
|
| |
5
|
|
 |
6
|
Paul D. Gross , Ravishankar Arunachalam , Karthik Rajagopal , Lawrence T. Pileggi, Determination of worst-case aggressor alignment for delay calculation, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.212-219, November 08-12, 1998, San Jose, California, United States
[doi> 10.1145/288548.288616]
|
 |
7
|
|
 |
8
|
|
 |
9
|
Ying Liu , Lawrence T. Pileggi , Andrzej J. Strojwas, Model order-reduction of RC(L) interconnect including variational analysis, Proceedings of the 36th ACM/IEEE conference on Design automation, p.201-206, June 21-25, 1999, New Orleans, Louisiana, United States
[doi> 10.1145/309847.309914]
|
| |
10
|
|
 |
11
|
|
| |
12
|
A. Odabasioglu, M. Celik and L. T. Pileggi, "PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 8, August 1998, pp. 645--654.
|
 |
13
|
|
 |
14
|
|
| |
15
|
M. Orshansky, L. Milor, P. Chen, K. Keutzer, C. Hu, "Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, pp. 544--553.
|
| |
16
|
L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. on Computer-Aided Design, vol 9, April 1990, pp. 352--366.
|
| |
17
|
Y. Sasaki and G. D. Micheli, "Crosstalk Delay Analysis using Relative Window Method," in Proc. IEEE ASIC/SoC Conference, 1999, pp. 9--13.
|
| |
18
|
T. Sato, Y. Cao, D. Sylvester and C. Hu, "Characterization of Interconnect Coupling Noise using In-situ Delay-Change Curve Measurement," in Proc. IEEE ASIC/SoC Conference, 2000, pp. 321--325.
|
 |
19
|
|
 |
20
|
C. Visweswariah , K. Ravindran , K. Kalafala , S. G. Walker , S. Narayan, First-order incremental block-based statistical timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
[doi> 10.1145/996566.996663]
|
|