Impact of interconnect resistance increase on system performance of low power and high performance designs

ABSTRACT

The scaling of Cu/Low-k interconnects into the deep submicron (DSM) regime is characterized by a significant increase in resistance. This increase is caused by geometrical scaling of interconnect dimensions, the non-scalability of high resistivity diffusion barrier and the resistivity increase due to surface and grain-boundary scattering of charge carrying electrons. The resistance of interconnects impacts the delay of the circuits and consequently the performance of chips. We investigate the impact of this phenomenon on system level performance for low power and high performance applications. It results that (a) it is important to consider the resistivity increase early in design phase to maximize the performance of the chips and (b) it is possible to optimally trade-off between various metrics of interest such as clock frequency, chip energy and chip area by exploring the freedom in choosing different interconnect process technology options.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)

General Terms:
Design, Performance

Keywords:
interconnect sizing, interconnect technology evaluation, power-delay trade-off, wire sizing