Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture

ABSTRACT

The increasing gap between design productivity and chip complexity, and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable Intellectual Property (IP) cores. The physical design implementation of the macro cells (IP blocks or pre-designed blocks) in general needs to find a well balanced solution among chip area, on-chip interconnect energy and critical path delay. We are especially interested in the entire trade-off curve among these three criteria at the floorplanning stage. We show this concept for a real communication scheme based on segmented bus, rather than just an extreme solution. A fast exploration design flow from the memory organization to the final layout is introduced to explore the design space.

REFERENCES

• 1: ARM AMBA bus specification. http://www.arm.com/armwww.ns4/html/AMBA?OpenDocument.
• 2: Blast chip 4.0 user guide. Magma Design Automation, pages 271--351.
• 3: ST Bus specifications. http://www.stmcu.com/inchtml-pages-STBus_intro.html.
• 4: Fixed-Outline Floorplanning through Better Local Search, Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors, p.328, September 23-26, 2001
• 5: Saurabh N. Adya , Igor L. Markov, Consistent placement of macro-blocks using floorplanning and standard-cell placement, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA [doi>10.1145/505388.505392]
• 6: A. Papanikolaou, F. Starzer, M. Miranda, F. Catthoor, and K. Bosschere. Architectural and physical design optimizations for efficient intra-tile communication. In Intnl. System-on Chip Symp. (SoC) Conference Proceedings, November 2005.
• 7: Luca Benini , Giovanni De Micheli, Networks on Chips: A New SoC Paradigm, Computer, v.35 n.1, p.70-78, January 2002 [doi>10.1109/2.976921]
• 8: Francky Catthoor , Eddy de Greef , Sven Suytack, Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design, Kluwer Academic Publishers, Norwell, MA, 1998
• 9: J. Y. Chen , W. B. Jone , J. S. Wang , H.-I. Lu , T. F. Chen, Segmented bus design for low-power systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.1, p.25-29, March 1999 [doi>10.1109/92.748197]
• 10: K. Heyrman, A. Papanikolaou, F. Catthoor, P. Veelaert, and W. Philips. Energy costs of transporting switch control bits for a segmented bus. In proRISC 2005 Conference Proceedings, 2005.
• 11: Huaiyu Xu , Maogang Wang , Bo-Kyung Choi , Majid Sarrafzadeh, A Trade-off Oriented Placement Tool, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.467, November 09-13, 2003 [doi>10.1109/ICCAD.2003.23]
• 12: Jingcao Hu , Yangdong Deng , Radu Marculescu, System-Level Point-to-Point Communication Synthesis Using Floorplanning Information, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.573, January 07-11, 2002
• 13: M.A. Jimenez and M. Shanblatt. Integrating a low-power objective into the placement of macro block-based layouts. In MWSCAS 2001 Conference Proceedings, pages 62--65, August 2001.
• 14: M. McFarland. A fast floor planning algorithm for architectural evaluation. In International Conference on Computer Design Conference Proceedings, pages 96--99, October 1989.
• 15: Fan Mo , Abdallah Tabbara , Robert K. Brayton, A force-directed macro-cell placer, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
• 16: V. Moshnyage and K. Tamaru. A placement driven methodology for high-level synthesis of sub-micron asic's. ISCAS, 4:12--15, May 1996.
• 17: H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. Vlsi module placement based on rectangle packing by the sequence pare. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, 15(12):1518--1524, December 1996.
• 18: A. Papanikolaou, K. Koppenberger, and M. Miranda. Memory communication network exploration for low-power distributed memory organisations. In IEEE Wsh. on Signal Processing Systems (SIPS) Conference Proceedings, pages 176--181. IEEE Press, October 2004.
• 19: G. Pei-Ning, T. Takahashi, C. Chung-Kuan, and T. Yoshimura. Floorplanning using a tree representation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and System, 20(2):281--289, February 2001.
• 20: Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

General Terms:
Design

Keywords:
floorplanning, segmented bus, trade-offs