Modeling and analysis of the system bus latency on the SoC platform

ABSTRACT

In the SoC, the system bus makes a bottleneck for data communication in high speed on a chip. In addition, the system allows multiple bus layers for efficient management of the bus resources on a SoC. In this paper, we present a latency model of the shared bus connecting multiple IPs. Using the latency model, we analyzed the latencies of the system bus on a SoC to get a throughput needed for the system. This result is used as a criterion for setting optimal bus architecture for a specific SoC design. We get latencies for examples MPEG and USB 2.0 using the proposed latency model and compare with the simulation result from MaxSim tools. As a result, the accuracy of the latency model for a single layer and multiple layers is over 96% and 85%, respectively.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Topology (e.g., bus, point-to-point)

General Terms:
Experimentation

Keywords:
SoC, latency, multi-layer bus, platform, system bus