Statistical analysis and optimization in the presence of gate and interconnect delay variations

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Statistical analysis and optimization in the presence of gate and interconnect delay variations

Full text

Pdf (55 KB)

Source

International Workshop on System-Level Interconnect Prediction archive
Proceedings of the 2006 international workshop on System-level interconnect prediction table of contents

Munich, Germany

SESSION: Design for manufacturability table of contents

Pages: 37 - 37

Year of Publication: 2006

ISBN:1-59593-255-0

Author

Chandu Visweswariah

IBM Thomas J. Watson Research Center, Yorktown Heights, NY

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 16, Citation Count: 2

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/1117278.1117287 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Hongliang Chang , Sachin S. Sapatnekar, Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.621, November 09-13, 2003 [doi>10.1109/ICCAD.2003.129]
	2	M. R. Guthaus, N. Venkateswaran, C. Visweswariah, and V. Zolotov. Gate sizing using incremental parameterized statistical timing analysis. IEEE International Conference on Computer-Aided Design, pages 1029--1036, November 2005. San Jose, CA.
	3	Chandu Visweswariah, Death, taxes and failing chips, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775921]
	4	C. Visweswariah , K. Ravindran , K. Kalafala , S. G. Walker , S. Narayan, First-order incremental block-based statistical timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996663]
	5	J. Xiong, V. Zolotov, C. Visweswariah, and N. Venkateswaran. Criticality computation in parameterized statistical timing. Proc. 2006 TAU (ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems), February 2006. San Jose, CA, submitted for review.
	6	J. Xiong, V. Zolotov, C. Visweswariah, and N. Venkateswaran. Criticality computation in parameterized statistical timing. Proc. 2006 Design Automation Conference, July 2006. San Francisco, CA, submitted for review.
	7	P. S. Zuchowski , P. A. Habitz , J. D. Hayes , J. H. Oppold, Process and environmental variation impacts on ASIC timing, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.336-342, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382597]

CITED BY 2

	I-Jye Lin , Tsui-Yee Ling , Yao-Wen Chang, Statistical circuit optimization considering device andinterconnect process variations, Proceedings of the 2007 international workshop on System level interconnect prediction, March 17-18, 2007, Austin, Texas, USA
	I-Jye Lin , Yao-Wen Chang, An efficient algorithm for statistical circuit optimization using Lagrangian relaxation, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California