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A tale of two nets: studies of wirelength progression in physical design
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Source International Workshop on System-Level Interconnect Prediction archive
Proceedings of the 2006 international workshop on System-level interconnect prediction table of contents
Munich, Germany
SESSION: Prediction of individual wire properties table of contents
Pages: 17 - 24  
Year of Publication: 2006
ISBN:1-59593-255-0
Authors
Andrew B. Kahng  University of California, San Diego, La Jolla, CA
Sherief Reda  University of California, San Diego, La Jolla, CA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

At every stage in physical design, engineers are faced with many different objectives and tools to develop, optimize, and evaluate their design. Each choice of a tool or an objective to optimize can potentially lead to a completely different final physically designed circuit. Furthermore, some of the objectives optimized by the tools are not necessarily the best or right objectives, but rather compromised objectives; for example, placers optimize the half-perimeter wirelength rather than the routed wirelength. The contributions of this paper are twofold. First, we define and use a metric to measure the consistency of optimizing wirelength during the different stages of physical design. Our main technique is based on tracing the relative lengths of two nets - or more accurately pairs of nets - as they progress through the physical design flow. Second, we propose a simple method to quantify the similarity between the results of different tools. Our empirical results point out to the physical design stages where vulnerability can occur from optimizing compromised objectives.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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J. Cong and S. K. Lim, "Edge Separability-Based Circuit Clustering With Application to Multilevel Circuit Partitioning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23(3), pp. 346--357, 2004.
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A. B. Kahng, S. Reda, and Q. Wang, "Architecture and Details of a High Quality, Large-Scale Analytical Placer," in Proc. IEEE International Conference on Computer Aided Design, 2005, pp. 891--898.
 
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A. B. Kahng and S.Reda, "Intrinsic Shortest Path Length: A New, Accurate A Priori Wirelength Estimator," in Proc. IEEE International Conference on Computer Aided Design, 2005, pp. 173--180.
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M. Queyranne, "Performance Ratio of Polynomial Heuristics for Triangle Inequality Quadratic Assignment Problem," Operations Research Letters, vol. 4, p. 1986, 231--342.
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T. Taghavi, X. Yang, B. K. Choi, M. Wang, and M. Sarrafzadeh, "DRAGON2005: Large-Scale Mixed-Size Placement Tool," in Proc. ACM/IEEE International Symposium on Physical Design, 2001, pp. 245--247.
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X. Yan, B. K. Choi, and M. Sarrafzadeh, "Routabtility Driven White Space Allocation for Fixed-Die Standard-Cell Placement," in Proc. ACM/IEEE International Symposium on Physical Design, 2002, pp. 42--47.


Collaborative Colleagues:
Andrew B. Kahng: colleagues
Sherief Reda: colleagues