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ABSTRACT

We also study a clustering technique for a cluster-based FPGA to optimize the routability of outer cluster nets. Prior research of FPGA clustering aims to take in inter-cluster connections to utilize the various advantages of the local interconnection in the cluster. Taking in the inter-cluster connections to the cluster can improve the FPGA speed and area, and can lighten the burden of the placement and routing tool. However, many inter-cluster connections still remain in the outside cluster. The condition of these connections give the performance of the circuit big influence. Therefore, we propose the effective clustering technique to optimize routability of outer cluster nets which are not taken in. In order to reduce the used routing resources in FPGA, our technique uses two evaluation functions. One evaluation function can be reduced routing resources in the outside cluster. The second evaluation function can utilize various characteristics of the local routing resources in the inside cluster. Our clustering technique has the unusual ability in the optimization of routing resources concurrently. As a result, our method resulted in 21.4% improvement in terms of the routing area (16.6% on average), and the critical path delay is reduced by 28.0% (11.8% on average) compared to existing clustering method in the benchmark circuits.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids