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Fine-grained island style architecture for molecular electronic devices
Source International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays table of contents
Monterey, California, USA
POSTER SESSION: Architecture table of contents
Pages: 226 - 226  
Year of Publication: 2006
ISBN:1-59593-292-5
Authors
Mohammad Tehranipoor  UMBC, CSEE, Baltimore, MD
Reza M. Rad  UMBC, CSEE, Baltimore, MD
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper a fine-grained island style architecture is proposed based on crossbars of nanowires with diode-logic created by molecular devices. A multiple-bit access mechanism is the main requirement for the clusters in every island style architecture to provide inputs, outputs and configuration bits. Island style FPGA architecture with its rich interconnect capabilities seems to be a proper choice for high-level architectures in nanoscale devices. Providing appropriate access to all clusters inside such architectures to communicate with input, output and configuration signals is the main requirement in these structures. In this paper, a multiple-bit DMUX scheme is proposed to act as CMOS-Nano interface and facilitate the configuration and input/output transfer to the nanoscale crossbar structure of the clusters. Two different architectures for the multiple-bit DMUX are proposed. The first DMUX architecture uses nano-imprint technology to provide the required interconnections between nanowires in the architecture and hence is completely nanoscale while the second architecture uses CMOS wires as select lines of the DMUX. These two architectures are analyzed in terms of area overhead based on the number of CMOS and nanoscale wires used in them. The calculations show that both approaches are area efficient when compared to their CMOS counterpart. The estimates also show that for a wide variety of cluster sizes, area of a cluster, that can be configured as large number of lookup tables (LUTs), is significantly smaller than a single 4-input CMOS LUT (22 nm technology). The proposed nano architecture also has its novelty in structure of the clusters and the way these clusters can be used to implement multiple logic functions on them.



Collaborative Colleagues:
Mohammad Tehranipoor: colleagues
Reza M. Rad: colleagues