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ABSTRACT
A key advantage of soft processors (processors built on an FPGA programmable fabric) over hard processors is that they can be customized to suit an application program's specific software. This notion has been exploited in the past principally through the use of application-specific instructions. While commercial soft processors are now widely deployed, they are available in only a few microarchitectural variations. In this work we explore the advantage of tuning the processor's microarchitecture to specific software applications, and show that there are significant advantages in doing so.Using an infrastructure for automatically generating soft processors that span the area/speed design space (while remaining competitive with Altera's Nios II variations), we explore the impact of tuning several aspects of microarchitecture including: (i) hardware vs software multiplication support; (ii) shifter implementation; and (iii) pipeline depth, organization, and forwarding. We find that the processor design that is fastest overall (on average across our embedded benchmark applications) is often also the fastest design for an individual application. However, in terms of area efficiency (i.e., performance-per-area), we demonstrate that a tuned microarchitecture can offer up to 30% improvement for three of the benchmarks and on average 11.4% improvement over the fastest-on-average design. We also show that our benchmark applications use only 50% of the available instructions on average, and that a processor customized to support only that subset of the ISA for a specific application can on average offer 25% savings in both area and energy. Finally, when both techniques for customization are combined we obtain an average improvement in performance-per-area of 25%.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
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ARCtangent. http://www.arc.com.
|
| |
2
|
Dhrystone 2.1. http://www.freescale.com.
|
| |
3
|
MicroBlaze. http://www.xilinx.com/microblaze.
|
| |
4
|
Nios II. http://www.altera.com/roducts/ip/rocessors/nios2.
|
| |
5
|
RATES - A Reconfigurable Architecture TEsting Suite. http://www.eecg.utoronto.ca/~lesley/benchmarks/rates/.
|
| |
6
|
Stretch. http://www.stretchinc.com.
|
| |
7
|
XiRisc. http://www.micro.deis.unibo.it/~campi/XiRisc/.
|
| |
8
|
Xtensa. http://www.tensilica.com.
|
| |
9
|
R. Cliff. Altera Corporation. Private Comm, 2005.
|
| |
10
|
R. Dimond, O. Mencer, and W. Luk. CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools. In International Conference on Field Programmable Logic (FPL), August 2005.
|
| |
11
|
M. Guthaus and et al. MiBench: A free, comercially representative embedded benchmark suite. In Proc. IEEE 4th Annual Workshop on Workload Characterisation December 2001.
|
| |
12
|
M. Itoh, S. Higaki, J. Sato, A. Shiomi, Y. Takeuchi, A. Kitajima, and M. Imai. PEAS-III: An ASIP Design Environment, September 2000.
|
 |
13
|
David Lewis , Vaughn Betz , David Jefferson , Andy Lee , Chris Lane , Paul Leventis , Sandy Marquardt , Cameron McClintock , Bruce Pedersen , Giles Powell , Srinivas Reddy , Chris Wysocki , Richard Cliff , Jonathan Rose, The stratixπ routing and logic architecture, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
[doi> 10.1145/611817.611821]
|
| |
14
|
P. Metzgen. Optimizing a High-Performance 32-bit Processor for Programmable Logic. In International Symposium on System-on-Chip 2004.
|
| |
15
|
|
| |
16
|
K. Morris. Embedded Dilemma. http://www.fpgajournal.com/articles/embedded.htm, November 2003.
|
| |
17
|
J. Turley. Survey: Who uses custom chips. Embedded Systems Programming August 2005.
|
| |
18
|
P. Yiannacouras. SPREE. http://www.eecg.utoronto.ca/~yiannac/SPREE/.
|
| |
19
|
P. Yiannacouras. The Microarchitecture of FPGA-Based Soft Processors. Master's thesis, University of Toronto, 2005. http://www.eecg.toronto.edu/~jayar/pubs/theses/Yiannacouras/PeterYiannacouras.pdf.
|
 |
20
|
Peter Yiannacouras , Jonathan Rose , J. Gregory Steffan, The microarchitecture of FPGA-based soft processors, Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, September 24-27, 2005, San Francisco, California, USA
[doi> 10.1145/1086297.1086325]
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CITED BY 10
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David Sheldon , Rakesh Kumar , Roman Lysecky , Frank Vahid , Dean Tullsen, Application-specific customization of parameterized FPGA soft-core processors, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
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Scott Sirowy , Yonghui Wu , Stefano Lonardi , Frank Vahid, Two-level microprocessor-accelerator partitioning, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
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Shih-Lien L. Lu , Peter Yiannacouras , Rolf Kassa , Michael Konow , Taeweon Suh, An FPGA-based Pentium® in a complete desktop system, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, February 18-20, 2007, Monterey, California, USA
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Peter Yiannacouras , J. Gregory Steffan , Jonathan Rose, VESPA: portable, scalable, and flexible FPGA-based vector processors, Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, October 19-24, 2008, Atlanta, GA, USA
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INDEX TERMS
Primary Classification:
C.
Computer Systems Organization
C.1
PROCESSOR ARCHITECTURES
C.1.3
Other Architecture Styles
Subjects:
Adaptable architectures
General Terms:
Design,
Measurement,
Performance
Keywords:
ASIP,
FPGA,
Nios,
RTL generation,
SPREE,
application specific,
customization,
embedded processor,
microarchitecture,
soft processor
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