An adaptive Reed-Solomon errors-and-erasures decoder

ABSTRACT

The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful defense against burst data errors, the significant circuit area and power consumption of customized RS decoder hardware can be limiting for embedded computing environments. To support enhanced performance decoding with minimal power consumption, a dynamically-reconfigurable FPGA-based Reed-Solomon decoder has been developed. Our errors-and-erasures decoding system uses multiple erasure blocks to identify the location of likely corrupted data and multiple decoders to attempt error correction. The RS decoder design is implemented in reconfigurable hardware to leverage architectural parallelism and specialization. Run-time dynamic reconfiguration of the decoding system is used in response to variations in channel conditions to support the fastest possible data rate while, as a secondary metric, minimizing decoder power consumption. Algorithm parameters for the decoding system have been determined via simulation and the design has been implemented in Altera Stratix FPGAs. Through experimentation using an Altera 1S40 Stratix FPGA, we show that dynamic reconfiguration can result in an 14% performance improvement versus a non-reconfigurable decoder implementation. Comparisons with a Pentium IV microprocessor illustrate five orders of magnitude performance improvement.

REFERENCES

• 1: Altera Corporation. Nios Stratix Development Kit, July 2003.
• 2: Altera Corporation. Stratix Data Sheet, May 2003.
• 3: L. Atieno. Run-time Dynamically Reconfigurable Reed-Solomon Decoder System. Master's thesis, Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, Feb. 2005.
• 4: C. W. Baum and M. Pursley. Bayesian generation of dependent erasures for frequency-hop communications and fading channels. IEEE Transactions on Communications, 44(12):1720--1729, Dec. 1996.
• 5: C. W. Baum and C. S. Wilkins. Erasure generation and interleaving for meteor-burst communications with fixed-rate and variable-rate coding. IEEE Transactions on Communications, 45(6):625--628, June 1997.
• 6: A. Haase, M. Boden, and M. Langer. Design of a Reed Solomon Decoder Using Partial Dynamic Reconfiguration of XILINX VIRTEX FPGAs - A Case Study. In Design, Automation and Test in Europe, Mar. 2002.
• 7: D. Lee, S. Lee, and J. Kim. A Reed-Solomon decoder with efficient recursive cell architecture for DVD application. In IEEE International Conference on Consumer Electronics, pages 184--185, 2001.
• 8: Hanho Lee, High-speed VLSI architecture for parallel Reed-Solomon decoder, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.2, p.288-294, April 2003 [doi>10.1109/TVLSI.2003.810782]
• 9: S. Li, K. Pan, J. Yuan, A. Vigil, and A. Berg. Adaptive Reed-Solomon coding for wireless ATM communications. In IEEE Southeastcon, pages 27--30, Apr. 2000.
• 10: S. Lin and D. J. Costello. Error Control Coding: Fundamentals and Applications. Prentice Hall, Englewood Cliffs, NJ, 1983.
• 11: Micron Technology, Inc. MT48LC4M32B2 SDRAM Data Sheet, Apr. 2003.
• 12: S. Nanda, K. Balachandran, and S. Kumar. Adaptation techniques in wireless packet data services. IEEE Communications Magazine, 38(1):54--64, Jan. 2000.
• 13: K. Oh and W. Sung. An Efficient Reed-Solomon Decoder VLSI with Erasure Correction. In IEEE Workshop on Signal Processing Systems, pages 193--201, Nov. 1997.
• 14: Theodore S. Rappaport, Wireless Communications: Principles and Practice, IEEE Press, Piscataway, NJ, 1996
• 15: M. K. Song, E. B. Kim, H. S. Won, and M. H. Kong. Architecture For Decoding Adaptive Reed-Solomon Codes with Variable Block Length. IEEE Transactions on Consumer Electronics, 48(3):631--637, Aug. 2002.
• 16: Stephen B. Wicker, Reed-Solomon Codes and Their Applications, IEEE Press, Piscataway, NJ, 1994

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS

General Terms:
Design

Keywords:
FPGA, Reed-Solomon, power reduction