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Multithreaded architectures and the sort benchmark
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Source Data Management On New Hardware archive
Proceedings of the 1st international workshop on Data management on new hardware table of contents
Baltimore, Maryland
SESSION: Best paper award table of contents
Article No. 1  
Year of Publication: 2005
Author
Phil Garcia  Lehigh University
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 13,   Downloads (12 Months): 103,   Citation Count: 2
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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[5] J. Dongarra, K. London, S. Moore, P. Mucci, and D. Terpstra. Using PAPI for hardware performance monitoring on Linux systems. In Conference on Linux Clusters: The HPC Revolution, June 2001.
 
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[7] P. C. Garcia and H. F. Korth. Hash-join algorithms on modern multithreaded computer architectures. Technical Report LU-CSE-05-001, Lehigh Univ., 2005.
 
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[9] G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker, and P. Roussel. The microarchitecture of the Pentium 4 processor. Intel Technology Journal, (Q1), 2001.
 
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[10] Intel. Intel Pentium 4 Processor Optimization, 2001.
 
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[14] D. T. Marr, F. Binns, D. L. Hill, G. Hinton, D. A. Koufaty, J. A. Miller, and M. Upton. Hyper-threading technology architecture and microarchitecture. Intel Technology Journal, (Q1):4-15, 2002.
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[16] C. Nyberg, J. Gray, and C. Koester. A minute with Nsort on a 32P NEC Windows Itanium2 server. Technical report, Microsoft Research, April 2004.
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[21] H. Wang, P. H. Wang, R. D. Weldon, S. M. Ettinger, H. Saito, M. Girkar, S. S. Liao, and J. P. Shen. Speculative precomputation: Exploring the use of multithreading for latency. Intel Technology Journal, (Q1):22-35, 2002.