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Compiler-directed high-level energy estimation and optimization
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ACM Transactions on Embedded Computing Systems (TECS) archive
Volume 4 ,  Issue 4  (November 2005) table of contents
Pages: 819 - 850  
Year of Publication: 2005
ISSN:1539-9087
Authors
I. Kadayif  The Pennsylvania State University, University Park, PA
M. Kandemir  The Pennsylvania State University, University Park, PA
G. Chen  The Pennsylvania State University, University Park, PA
N. Vijaykrishnan  The Pennsylvania State University, University Park, PA
M. J. Irwin  The Pennsylvania State University, University Park, PA
A. Sivasubramaniam  The Pennsylvania State University, University Park, PA
Publisher
ACM  New York, NY, USA
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ABSTRACT

The demand for high-performance architectures and powerful battery-operated mobile devices has accentuated the need for power optimization. While many power-oriented hardware optimization techniques have been proposed and incorporated in current systems, the increasingly critical power constraints have made it essential to look for software-level optimizations as well. The compiler can play a pivotal role in addressing the power constraints of a system as it wields a significant influence on the application's runtime behavior. This paper presents a novel Energy-Aware Compilation (EAC) framework that estimates and optimizes energy consumption of a given code, taking as input the architectural and technological parameters, energy models, and energy/performance/code size constraints. The framework has been validated using a cycle-accurate architectural-level energy simulator and found to be within 6% error margin while providing significant estimation speedup. The estimation speed of EAC is the key to the number of optimization alternatives that can be explored within a reasonable compilation time. As shown in this paper, EAC allows compiler writers and system designers to investigate power-performance tradeoffs of traditional compiler optimizations and to develop energy-conscious high-level code transformations.


REFERENCES

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Bodin, F., Chamski, Z., Eisenbeis, C., Rohou, E., and Seznec, A. 1998. Gcds: A compiler strategy for trading code size against performance in embedded applications. Tech. Rep. RR-3346, INRIA, Rocquencourt, France. Jan.
 
7
8
 
9
Burger, D., Austin, T., and Bennett, S. 1996. Evaluating future microprocessors: The simplescalar tool set. Tech. Rep. CS-TR-96-103, (July). Computer Science Dept., University of Wisconsin, Madison, WI.
10
 
11
 
12
 
13
 
14
15
 
16
 
17
 
18
19
20
21
 
22
Gonzales, R. and Horowitz, M. 1996. Energy dissipation in general purpose processors. IEEE Journal of Solid-State Circuits 31, 9 (Sept.), 1277--1283.
 
23
24
 
25
Irwin, M. J. and Vijaykrishnan, N. 2000. Low power design: From soup to nuts. In Tutorial Notes, ISCA' 2000.
 
26
27
 
28
 
29
30
31
32
33
34
 
35
Lorch, J. R. and Smith, A. J. 1998. Software strategies for portable computer energy management. IEEE Personal Communications, 60--73.
36
37
38
39
40
 
41
Musoll, E. 2000. Estimation of the upper-bound useless energy dissipation in a high-performance processor. Kool-Chips.
 
42
43
44
 
45
46
 
47
Schwab, H. 2004. lp_solve mixed integer linear program solver. ftp://ftp.es.ele.tue.nl/pub/lp_solve/.
 
48
Shiue, W.-T. and Chakrabarti, C. 1999. Memory exploration for low power, embedded systems. Tech. Rep. CLPE-TR-9-1999-20, Arizona State University, AZ.
49
 
50
 
51
52
53
 
54
 
55
Toburen, M. C., Conte, T. M., and Reilly, M. 1998. Instruction scheduling for low power dissipation in high performance processors. In Proc. the Power Driven Micro-architecture Workshop in conjunction with the ISCA'98, Barcelona, Spain.
56
57
 
58
Viswanath, R., Wakharkar, V., Watwe, A., and Lebonheur, V. 2000. Thermal performance challenges from silicon to systems. Intel Technology Journal Q3.
 
59
Willems, M. and Zivojnovic, V. 1996. DSP-compiler: Product quality for control oriented applications? In Proc. ICSPAT'96. 752--756.
 
60
61
62
 
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Collaborative Colleagues:
I. Kadayif: colleagues
M. Kandemir: colleagues
G. Chen: colleagues
N. Vijaykrishnan: colleagues
M. J. Irwin: colleagues
A. Sivasubramaniam: colleagues