High-level synthesis: an essential ingredient for designing complex ASICs

ABSTRACT

It is common wisdom that synthesizing hardware from higher-level descriptions than Verilog incurs a performance penalty. The case study here shows that this need not be the case. If the higher-level language has suitable semantics, it is possible to synthesize hardware that is competitive with hand-written Verilog RTL. Differences in the hardware quality are dominated by architecture differences and, therefore, it is more important to explore multiple hardware architectures. This exploration is not practical without quality synthesis from higher-level languages.

REFERENCES

• 1: Arvind , Xiaowei Shen, Using Term Rewriting Systems to Design and Verify Processors, IEEE Micro, v.19 n.3, p.36-46, May 1999 [doi>10.1109/40.768501]
• 2: [2] AUGUSTSSON, L., SCHWARZ, J., AND NIKHIL, R. S. Bluespec Language Definition, 2001. Sandburst Corp.
• 3: R. J. R. Back , R. Kurki-Suonio, Decentralization of process nets with centralized control, Proceedings of the second annual ACM symposium on Principles of distributed computing, p.131-142, August 17-19, 1983, Montreal, Quebec, Canada [doi>10.1145/800221.806716]
• 4: [4] BLUESPEC, INC. Interra Systems' Benchmarking of Bluespec Compiler Uncovers No Compromises in Quality of Results (QoR), May 3 2004. www.bluespec.com/news/press.htm, www.bluespec.com/images/pdfs/InterraReport042604.pdf.
• 5: K. Mani Chandy, Parallel program design: a foundation, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1988
• 6: [6] DAVE, N. Designing a Reorder Buffer in Bluespec. In Proc. MEMOCODE'04 (June 2004).
• 7: David L. Dill, The Murphi Verification System, Proceedings of the 8th International Conference on Computer Aided Verification, p.390-393, August 03, 1996
• 8: Daniel D. Gajski , Nikil D. Dutt , Allen C.-H. Wu , Steve Y.-L. Lin, High-level synthesis: introduction to chip and system design, Kluwer Academic Publishers, Norwell, MA, 1992
• 9: [9] GAJSKI, D. SpecC: Specification Language and Methodology. Kluwer Academic, Boston, 2000.
• 10: [10] HOE, J. C. Operation-Centric Hardware Description and Synthesis. PhD thesis, MIT, June 2000.
• 11: James C. Hoe , Arvind, Synthesis of operation-centric hardware descriptions, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
• 12: Leslie Lamport, Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 2002
• 13: [13] NORDIN, G., AND HOE, J. C. Synchronous Extensions to Operation-Centric Hardware Description Languages. In Proc. MEMOCODE'04 (June 2004).
• 14: Juha Plosila , Kaisa Sere, Action Systems in Pipelined Processor Design, Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems, p.156, April 07-10, 1997
• 15: [15] ROSENBAND, D. L. The Ephemeral History Register: Flexible Scheduling for Rule-Based Designs. In Proc. MEMOCODE'04 (June 2004).
• 16: Daniel L. Rosenband , Arvind, Modular scheduling of guarded atomic actions, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996583]
• 17: J. Staunstrup , M. R. Greenstreet, From high-level descriptions to VLSI circuits, BIT, v.28 n.3, p.620-638, 1988 [doi>10.1007/BF01941138]
• 18: [18] SYNOPSYS. Behavioral Compiler/Behavioral Synthesis. www.synopsys.com/products/beh_syn/beh_syn.html.