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Dynamic range estimation for nonlinear systems
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Source International Conference on Computer Aided Design archive
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design table of contents
Pages: 660 - 667  
Year of Publication: 2004
ISBN:0-7803-8702-3
Authors
Bin Wu  Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Jianwen Zhu  Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
F. N. Najm  Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Publisher
IEEE Computer Society  Washington, DC, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 22,   Citation Count: 2
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DOI Bookmark: 10.1109/ICCAD.2004.1382658

ABSTRACT

It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore the overall circuit area, delay and power consumption. While recent advances in analytical dynamic range estimation can deliver results accurate enough to account for both spatial and temporal correlation, the reported methods are only valid for linear systems. In this paper, we use a powerful mathematical tool, called polynomial chaos, which enables not only the orthogonal decomposition of random processes, but also the propagation of random processes through nonlinear systems with difficult constructs such as multiplications, divisions and conditionals. We show that when applied to interesting nonlinear applications such as adaptive filters, polynomial filters and rational filters, this method can produce complete, accurate statistics of each internal variable, thereby allowing the synthesis of bitwidth with the desired tradeoff between circuit performance and signal-to-noise ratio.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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[1] S. Mahlke, R. Ravindran, M. Schlansker, R. Schreiber, and T. Sherwood. Bitwidth cognizant architecture synthesis of custom hardware accelerators. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(11):1355-1371, November 2001.
 
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[21] P. Hall. The Bootstrap and Edgeworth Expansion. Springer-Verlag, Berlin/New York, NY, 1992.

Collaborative Colleagues:
Bin Wu: colleagues
Jianwen Zhu: colleagues
F. N. Najm: colleagues