Leakage control through fine-grained placement and sizing of sleep transistors

ABSTRACT

Leakage power is increasingly gaining importance with technology scaling. Multi-threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. Sleep transistor insertion in circuits is an effective application of MTCMOS technology for reducing leakage power. In This work we present a fine grained approach where each gate in the circuit is provided an independent sleep transistor. Key advantages of this approach include better circuit slack utilization and improvements in signal integrity (which is a major disadvantage in clustering based approaches). To this end, we propose an optimal polynomial time fine grained sleep transistor sizing algorithm. We also prove the selective sleep transistor placement problem as NP-complete and propose an effective heuristic. Finally, in order to reduce the sleep transistor area penalty (which might get high since clustering is not performed), we propose a placement area constrained sleep transistor sizing formulation. Our experiments show that on an average the sleep transistor placement and optimal sizing algorithm gave 69.7% and 59.0% savings in leakage power as compared to the conventional fixed delay penalty algorithms for 5 and 7% circuit slowdown respectively. Moreover the post placement area penalty was less than 5% which is comparable to clustering schemes according to Mohab Anis et al. (2003).

REFERENCES

• 1: Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Can recursive bisection alone produce routable placements?, Proceedings of the 37th conference on Design automation, p.477-482, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337549]
• 2: Benton H. Calhoun , Frank A. Honore , Anantha Chandrakasan, Design methodology for fine-grained leakage control in MTCMOS, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871535]
• 3: Changbo Long , Lei He, Distributed sleep transistor network for power reduction, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775879]
• 4: D. S. Hochbaum , J. George Shanthikumar, Convex separable optimization is not much harder than linear optimization, Journal of the ACM (JACM), v.37 n.4, p.843-862, Oct. 1990 [doi>10.1145/96559.96597]
• 5: [5] E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, A.L. Sangiovanni-Vincentelli. SIS: A System for Sequential Circuit Synthesis. Memorandum No. UCB/ERL M92/41, Department of EECS, UC Berkeley, May 1992.
• 6: Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
• 7: James Kao , Anantha Chandrakasan , Dimitri Antoniadis, Transistor sizing issues and tool for multi-threshold CMOS technology, Proceedings of the 34th annual conference on Design automation, p.409-414, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266182]
• 8: [8] J. Kao and A. Chandrakasan. "MTCMOS Sequential Circuits". In Procs of ESSDERC, Sept 2003.
• 9: James Kao , Siva Narendra , Anantha Chandrakasan, MTCMOS hierarchical sizing based on mutual exclusive discharge patterns, Proceedings of the 35th annual conference on Design automation, p.495-500, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277180]
• 10: [10] Mohab Anis et al. "Design and Optimization of Multithreshold CMOS (MTCMOS) Circuits". In IEEE Transactions on CAD of integrated Circuits and Systems, October 2003.
• 11: Pietro Babighian , Luca Benini , Enrico Macii, Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating, Proceedings of the conference on Design, automation and test in Europe, p.10720, February 16-20, 2004
• 12: Saibal Mukhopadhyay , Kaushik Roy, Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871549]
• 13: [13] S. Mutoh et al. "I-V Power Supply High Speed Digital Circuit Technology with Multithreshold-Voltage CMOS". In IEEE JSSC, vol. 30, no. 8, August 1995.