Fast flip-chip power grid analysis via locality and grid shells

ABSTRACT

Full-chip power grid analysis is time consuming. Several techniques have been proposed to tackle the problem but typically they deal with the power grid as a whole or partition at unnatural boundaries. Using a locality effect under flip-chip packaging, we propose a natural partitioning approach based on overlapping power grid "shells". The technique makes more efficient any previous simulation techniques that are polynomial in grid size. It is also parallelizable and therefore extremely fast. Using complete partitions gives no loss of accuracy compared to a full matrix solution, while lesser partitions are conservative for droop and current. Results on a recent Pentium/spl reg/ microprocessor design show excellent speed and accuracy.

REFERENCES

• 1: Howard H. Chen , David D. Ling, Power supply noise analysis methodology for deep-submicron VLSI chip design, Proceedings of the 34th annual conference on Design automation, p.638-643, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266307]
• 2: [2] E. Chiprout and T. V. Nguyen, "Power analysis of large interconnect grids with multiple sources using model reduction", Proceedings European Conference on Circuit Theory and Design, Stressa, Italy, Sept. 1999.
• 3: Janet M. Wang , Tuyen V. Nguyen, Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources, Proceedings of the 37th conference on Design automation, p.247-252, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337407]
• 4: Tsung-Hao Chen , Charlie Chung-Ping Chen, Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods, Proceedings of the 38th conference on Design automation, p.559-562, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379023]
• 5: [5] J. Kozhaya, S. R. Nassif, and F. N. Najm, "A multigrid-like technique for power grid analysis," IEEE Trans. On Computer-Aided Design, vol. 21, no. 10, pp. 1148-1160, 2002.
• 6: Haifeng Qian , Sani R. Nassif , Sachin S. Sapatnekar, Random walks in a supply network, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775860]
• 7: Abhijit Dharchoudhury , Rajendran Panda , David Blaauw , Ravi Vaidyanathan , Bogdan Tutuianu , David Bearden, Design and analysis of power distribution networks in PowerPC microprocessors, Proceedings of the 35th annual conference on Design automation, p.738-743, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277229]
• 8: [8] Dietrich Tönnies, "A Review and Trends in Flip-Chip Technology", Chip scale review, April 2004.