| Efficient statistical timing analysis through error budgeting |
| Full text |
Pdf
(777 KB)
|
| Source
|
International Conference on Computer Aided Design
archive
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
table of contents
Pages: 473 - 477
Year of Publication: 2004
ISBN:0-7803-8702-3
|
|
Authors
|
|
V. Khandelwal
|
Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
|
|
A. Davoodi
|
Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
|
|
A. Srivastava
|
Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
|
|
| Publisher |
IEEE Computer Society
Washington, DC, USA
|
| Bibliometrics |
Downloads (6 Weeks): 0, Downloads (12 Months): 14, Citation Count: 3
|
|
|
ABSTRACT
We propose a technique for optimizing the runtime in statistical timing analysis. Given a global acceptable error budget at the primary output which signifies the difference in the area of the accurate and approximate timing CDFs, we propose a formulation of budgeting this global error across all nodes in the circuit. This node error budget is used to simplify the computation of arrival time CDFs at each node using approximations. This simplification reduces the runtime of statistical timing analysis. We investigate two ways of exploiting this node error budget, firstly through piecewise linear approximation (see ibid., A. Devgan and C. Kashyap, 2003) and secondly though hierarchical quadratic approximation. Experimental results on ISCAS/MCNC benchmarks show that our approach is at most 3 times faster than accurate statistical timing analysis and had a very small error. We also found quadratic piecewise approximation to be more accurate than linear approximation but at lesser gains in runtime.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
 |
2
|
Aseem Agarwal , David Blaauw , Vladimir Zolotov , Sarma Vrudhula, Computation and Refinement of Statistical Bounds on Circuit Delay, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
[doi> 10.1145/775832.775922]
|
| |
3
|
[3] A. Agarwal, V. Zolotov and D. Blaauw. "Statistical Timing Analysis Using Bounds and Selective Enumeration". In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, Sept. 2003.
|
| |
4
|
|
 |
5
|
|
| |
6
|
[6] C. Visweswariah et al. "First-Order Parameterized Block-Based Statistical Timing Analysis". In Procs of TAU, 2004.
|
| |
7
|
[7] E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, A.L. Sangiovanni-Vincentelli. SIS: A System for Sequential Circuit Synthesis, Memorandum No. UCB/ERL M92/41, Department of EECS. UC Berkeley, May 1992.
|
| |
8
|
|
| |
9
|
[9] H. J. Bungartz. "Higher Order Finite Elements on Sparse Grids". In Technical Report SFB-Bericht Nr. 342/01/95 A, Institut fur Informatik, TU Munich 1995.
|
| |
10
|
[10] H. J. Bungartz and T. Dornseifer. "Sparse Grids: Recent Developments for Elliptic Partial Differential Equations". In Technical Report TUM-19702, SFB-Bericht Nr. 342/02/97 A, Institut fur Informatik, TU Munich 1997.
|
 |
11
|
J. A. G. Jess , K. Kalafala , S. R. Naidu , R. H. J. M. Otten , C. Visweswariah, Statistical timing for parametric yield prediction of digital integrated circuits, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
[doi> 10.1145/775832.776066]
|
| |
12
|
|
| |
13
|
|
|