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SILENT: serialized low energy transmission coding for on-chip interconnection networks
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Source International Conference on Computer Aided Design archive
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design table of contents
Pages: 448 - 451  
Year of Publication: 2004
ISBN:0-7803-8702-3
Authors
Kangmin Lee  Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Se-Joong Lee  Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Hoi-Jun Yoo  Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Publisher
IEEE Computer Society  Washington, DC, USA
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Downloads (6 Weeks): 0,   Downloads (12 Months): 10,   Citation Count: 3
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DOI Bookmark: 10.1109/ICCAD.2004.1382618

ABSTRACT

On-chip source-synchronous serial communication has many advantages over multi-bit parallel communication in the aspects of skew, crosstalk area cost, wiring difficulty, and clock synchronization. However, the serial wire tends to dissipate more energy than parallel bus due to the bit multiplexing. We propose a coding method to reduce the transmission energy of the serial communication by minimizing the number of transitions on the serial wire. We demonstrate the significant energy saving in a multimedia application, 3D graphics. We also apply the coding technique to a CMOS SoC implementation which integrates various processing units with packet switched on-chip networks.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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[1] S.J. Lee, et al., "An 800MHz Star-Connected On-Chip Network for Application to Systems on a Chip," ISSCC Dig. of Tech. Papers, pp. 468- 469, 2003.
 
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[2] B. Lau, et al., "A 2.6-GByte/s Multipurpose Chip-to-Chip Interface," Journal of Solid-State Circuits, vol. 33, no. 11, Nov. 1998.
 
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[3] S. Kimura, et al., "An On-Chip High Speed Serial Communication Method Based on Independent Ring Oscillators," ISSCC Dig. of Tech. Papers, pp. 390-391, 2003.
 
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[7] R. Woo, et al., "A 210mW Graphics LSI Implementing Full 3D Pipeline with 264Mtexels/s Texturing for Mobile Multimedia Applications," ISSCC Dig. of Tech. Papers, pp. 44-45, 2003.
 
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[8] K. Lee, et al., "A 51mW 1.6GHz Network for Low-Power Heterogeneous SoC Platfrom," ISSCC Dig. of Tech, Papers, pp. 152-153, 2004.

Collaborative Colleagues:
Kangmin Lee: colleagues
Se-Joong Lee: colleagues
Hoi-Jun Yoo: colleagues