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ABSTRACT
The Wisconsin Multifacet Project has created a simulation toolset to characterize and evaluate the performance of multiprocessor hardware systems commonly used as database and web servers. We leverage an existing full-system functional simulation infrastructure (Simics [14]) as the basis around which to build a set of timing simulator modules for modeling the timing of the memory system and microprocessors. This simulator infrastructure enables us to run architectural experiments using a suite of scaled-down commercial workloads [3]. To enable other researchers to more easily perform such research, we have released these timing simulator modules as the Multifacet General Execution-driven Multiprocessor Simulator (GEMS) Toolset, release 1.0, under GNU GPL [9].
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 60
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Michelle J. Moravan , Jayaram Bobba , Kevin E. Moore , Luke Yen , Mark D. Hill , Ben Liblit , Michael M. Swift , David A. Wood, Supporting nested transactional memory in logTM, ACM SIGPLAN Notices, v.41 n.11, November 2006
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Michael F. Spear , Arrvindh Shriraman , Luke Dalessandro , Sandhya Dwarkadas , Michael L. Scott, Nonblocking transactions without indirection using alert-on-update, Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures, June 09-11, 2007, San Diego, California, USA
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Jayaram Bobba , Kevin E. Moore , Haris Volos , Luke Yen , Mark D. Hill , Michael M. Swift , David A. Wood, Performance pathologies in hardware transactional memory, ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
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Nathan L. Binkert , Ronald G. Dreslinski , Lisa R. Hsu , Kevin T. Lim , Ali G. Saidi , Steven K. Reinhardt, The M5 Simulator: Modeling Networked Systems, IEEE Micro, v.26 n.4, p.52-60, July 2006
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Eric S. Chung , Eriko Nurvitadhi , James C. Hoe , Babak Falsafi , Ken Mai, A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
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Andrés Ortiz , Julio Ortega , Antonio F. Díaz , Pablo Cascón , Alberto Prieto, Protocol offload analysis by simulation, Journal of Systems Architecture: the EUROMICRO Journal, v.55 n.1, p.25-42, January, 2009
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John Wawrzynek , David Patterson , Mark Oskin , Shih-Lien Lu , Christoforos Kozyrakis , James C. Hoe , Derek Chiou , Krste Asanovic, RAMP: Research Accelerator for Multiple Processors, IEEE Micro, v.27 n.2, p.46-57, March 2007
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Ping Zhou , Bo Zhao , Yu Du , Yi Xu , Youtao Zhang , Jun Yang , Li Zhao, Frequent value compression in packet-based NoC architectures, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
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Jason Cong , Karthik Gururaj , Guoling Han , Adam Kaplan , Mishali Naik , Glenn Reinman, MC-Sim: an efficient simulation tool for MPSoC designs, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
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Marc Lupon , Grigorios Magklis , Antonio González, Version management alternatives for hardware transactional memory, Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture, p.69-76, October 26-26, 2008, Toronto, Canada
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Fuad Tabba , Mark Moir , James R. Goodman , Andrew W. Hay , Cong Wang, NZTM: nonblocking zero-indirection transactional memory, Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures, August 11-13, 2009, Calgary, AB, Canada
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Eric S. Chung , Michael K. Papamichael , Eriko Nurvitadhi , James C. Hoe , Ken Mai , Babak Falsafi, ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs, ACM Transactions on Reconfigurable Technology and Systems (TRETS), v.2 n.2, p.1-32, June 2009
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