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A chip prototyping substrate: the flexible architecture for simulation and testing (FAST)
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Source ACM SIGARCH Computer Architecture News archive
Volume 33 ,  Issue 4  (November 2005) table of contents
Special issue: dasCMP'05
SPECIAL ISSUE: Special issue: dasCMP'05 table of contents
Pages: 34 - 43  
Year of Publication: 2005
ISSN:0163-5964
Authors
John D. Davis  Stanford University
Stephen E. Richardson  Stanford University
Charis Charitsis  Stanford University
Kunle Olukotun  Stanford University
Publisher
ACM  New York, NY, USA
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ABSTRACT

We describe a hybrid hardware emulation environment: the Flexible Architecture for Simulation and Testing (FAST). FAST integrates field-programmable gate arrays (FPGAs), microprocessors, and memory to enable rapid prototyping of chip multiprocessors, multithreaded architectures, or other novel computer architectures and chip-level memory systems. FAST combines configurable and fixed-function hardware and software to facilitate rapid prototyping by utilizing components optimized for their particular tasks: FPGAs for interconnect and glue logic; processors for rapid program execution; and SRAMs for fast memory. Unlike software simulators, FAST can simulate complex designs at multi-megahertz speeds regardless of the simulation detail. We illustrate FAST's utility by describing mappings of both a small-scale CMP with speculation support and a large-scale CMP connected using a network. We then show performance results from a very simple, decoupled 4-way CMP executing small test programs.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
John D. Davis: colleagues
Stephen E. Richardson: colleagues
Charis Charitsis: colleagues
Kunle Olukotun: colleagues