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DBmbench: fast and accurate database workload representation on modern microarchitecture
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Source IBM Centre for Advanced Studies Conference archive
Proceedings of the 2005 conference of the Centre for Advanced Studies on Collaborative research table of contents
Toranto, Ontario, Canada
Pages: 254 - 267  
Year of Publication: 2005
ISSN:1705-7361
Authors
Minglong Shao  Database Group, Carnegie Mellon University
Anastassia Ailamaki  Database Group, Carnegie Mellon University
Babak Falsafi  Computer Architecture Laboratory, Carnegie Mellon University
Sponsors
NRC : National Research Council - Canada
: IBM Toronto Laboratory
: IBM Centre for Advanced Studies (CAS)
Publisher
IBM Press 
Bibliometrics
Downloads (6 Weeks): 8,   Downloads (12 Months): 45,   Citation Count: 9
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ABSTRACT

With the proliferation of database workloads on servers, much recent research on server architecture has focused on database system benchmarks. The TPC benchmarks for the two most common server workloads, OLTP and DSS, have been used extensively in the database community to evaluate the database system functionality and performance. Unfortunately, these benchmarks fall short of being effective in microarchitecture and memory system research due to several key shortcomings. First, setting up the experimental environment and tuning these benchmarks to match the workload behavior of interest involves extremely complex procedures. Second, the benchmarks themselves are complex and preclude accurate correlation of microarchitecture-and memory-level bottlenecks to dominant workload characteristics. Finally, industrial-grade configurations of such benchmarks are too large and preclude their use in detailed but slow microarchitectural simulation studies of future servers. In this paper, we first present an analysis of the dominant behavior in DSS and OLTP workloads, and highlight their key processor and memory performance characteristics. We then introduce a systematic scaling framework to scale down the TPC benchmarks. Finally, we propose the DBmbench, consisting of two substantially scaled-down benchmarks: µTPC-H and µTPC-C that accurately (> 95%) capture the processor and memory performance behavior of DSS and OLTP workloads.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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{4} L. A. Barroso, K. Gharachorloo, A. Nowatzyk, and B. Verghese. Impact of chip-level integration on performance of OLTP workloads. In Proceedings of International Symposium on High-Performance Computer Architecture, January 2000.
 
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{7} T. Diep, M. Annavaram, B. Hirano, and J. P. Shen. Analyzing performance characteristics of OLTP cached workloads by linear interpolation. In Workshop on Computer Architecture Evaluation using Commercial Workloads , September 2002.
 
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{10} IBM Corporation. IBM DB2 Universal Database Administration Guide: Implementation , 2000.
 
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{11} K. Keeton and D. A. Patterson. Towards a simplified database workload for computer architecture evaluations, chapter 4. Kluwer Academic Publishers, 2000.
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{17} SimpleScalar tool set. SimpleScalar LLC. http://www.simplescalar.com.
 
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{18} The Standard Performance Evaluation Corporation. SPEC CPU Benchmark. http://- www.specbench.org.
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{21} Transaction Processing Performance Countil. TPC benchmarks. http://www.tpc.org.
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CITED BY  9

Collaborative Colleagues:
Minglong Shao: colleagues
Anastassia Ailamaki: colleagues
Babak Falsafi: colleagues