The impact of traffic aggregation on the memory performance of networking applications

ABSTRACT

The trend of the networking processing is to increase the intelligence of the routers (i.e. security capacities). This means that there is an increment in the workload generated per packet and new types of applications are emerging, such as stateful programs. On the other hand, Internet traffic continues to grow vigorously. This fact involves an increment of the traffic aggregation levels and overloades the processing capacities of the routers.In this paper we show the importance of traffic aggregation level on networking application studies. We also classify the applications according to the data management of the packet processing. Hence, we present the different impacts on the data cache performance depending on the application category. Our results show that traffic aggregation level may affect the cache performance depending on the networking application category. Stateful applications show a significant sensitivity to this impact.

REFERENCES

• 1: Brian Caswell , James C. Foster , Ryan Russell , Jay Beale , Jeffrey Posluns, Snort 2.0 Intrusion Detection, Syngress Publishing, 2003
• 2: Cooperative association for internet data analysis. www.caida.org.
• 3: P. Chandra, F. Hady, R. Yavatkar, T. Bock, M. Cabot, and P. Mathew. Benchmarking network processors. In Proc. NP1, Held in conjunction with HPCA-8, Cambridge, MA, USA, Feb. 2002.
• 4: P. Crowley, M. A. Franklin, H. Hadimioglu, and P. Z. Onufryk. Network Processor Design: Issues and Practices, vol. 1, chapter Network Processors: An Introduction to Design Issues. Morgan Kaufmann Publishers, USA, 2002.
• 5: P. Crowley, M. A. Franklin, H. Hadimioglu, and P. Z. Onufryk. Network Processor Design: Issues and Practices, vol. 2, chapter Network Processors: Themes and Challenges. Morgan Kaufmann Publishers, USA, 2003.
• 6: Eddie Kohler , Jinyang Li , Vern Paxson , Scott Shenker, Observed structure of addresses in IP traffic, Proceedings of the 2nd ACM SIGCOMM Workshop on Internet measurment, November 06-08, 2002, Marseille, France [doi>10.1145/637201.637242]
• 7: Byeong Kil Lee , Lizy Kurian John, NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors, Proceedings of the 21st International Conference on Computer Design, p.226, October 13-15, 2003
• 8: S. Melvin, M. Nemirovsky, E. Musoll, J. Huynh, R. Milito, H. Urdaneta, and K. Saraf. A massively multithreaded packet processor. In Proc. of NP2, Held in conjunction with HPCA-9, CA, USA, 2003.
• 9: Gokhan Memik , William H. Mangione-Smith , Wendong Hu, NetBench: a benchmarking suite for network processors, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
• 10: A. Nemirovsky. Towards characterizing network processors: Needs and challenges. November 2000. Xstream Logic Inc., white paper.
• 11: National lab of applied network research. http://pma.nlanr.net/Traces.
• 12: A. M. Odlyzko. Internet traffic growth: Sources and implications. In Optical Transmission Systems and Equipment for WDM Networking II, B. B. Dingel, W. Weiershausen, A. K. Dutta, and K.-I. Sato, eds., Proc. SPIE, vol. 5247, Sep. 2003.
• 13: Ruoming Pang , Vern Paxson, A high-level programming environment for packet trace anonymization and transformation, Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications, August 25-29, 2003, Karlsruhe, Germany [doi>10.1145/863955.863994]
• 14: Amitabh Srivastava , Alan Eustace, ATOM: a system for building customized program analysis tools, Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation, p.196-205, June 20-24, 1994, Orlando, Florida, United States
• 15: J. Verdú, J. García, M. Nemrirovsky, and M. Valero. Analysis of traffic traces for stateful applications. In Proc. of NP3, Held in conjunction with HPCA-10, Madrid, Spain, February 2004.
• 16: T. Wolf and Mark A. Franklin. Commbench - a telecommunications benchmark for network processors. In Proc. of ISPASS, TX, USA, 2000.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Data-flow architectures
  C.2 COMPUTER-COMMUNICATION NETWORKS
      C.2.0 General
          Subjects: Data communications
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Performance attributes

General Terms:
Design, Performance, Theory