| Combining hardware and software cache coherence strategies |
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International Conference on Supercomputing
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Proceedings of the 5th international conference on Supercomputing
table of contents
Cologne, West Germany
Pages: 274 - 283
Year of Publication: 1991
ISBN:0-89791-434-1
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Authors
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David J. Lilja
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Center for Supercomputing Research and Development, University of Illinois at Urbana-Champaign, Urbana, Illinois
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Pen-Chung Yew
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Center for Supercomputing Research and Development, University of Illinois at Urbana-Champaign, Urbana, Illinois
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Downloads (6 Weeks): 1, Downloads (12 Months): 15, Citation Count: 7
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Allan Gottlieb , Ralph Grishman , Clyde P. Kruskal , Kevin P. McAuliffe , Larry Rudolph , Marc Snir, The NYU Ultracomputer—designing a MIMD, shared-memory parallel machine (Extended Abstract), Proceedings of the 9th annual symposium on Computer Architecture, p.27-42, April 26-29, 1982, Austin, Texas, United States
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A. Gupta, et al. "Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes," Int. Conf. Par. Proc., Vol. I, 1990, pp. 312-321.
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D. J. Kuck, et al. "Parallel Supercomputing Today and the Cedar Approach," Science, 28 Feb. 1986, pp. 967-974.
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D. J. Lilja and P.-C. Yew. "A Compiler-Assisted Directory-Based Cache Coherence Scheme", Univ. of Illinois, CSRD Rpt. No. 990, Nov. 1990.
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S. L. Min and J.-L. Baer. ~'A Timestamp-based Cache Coherence Scheme," Int. Conf. Par. Pro~., Vol. I, 1989, pp. 23-32.
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G. F. Pfister, et al. "The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture," Int. Conf. Par. Proc., 1985, pp. 764-771.
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