ACM Home Page
Please provide us with feedback. Feedback
Combining hardware and software cache coherence strategies
Full text PdfPdf (979 KB)
Source International Conference on Supercomputing archive
Proceedings of the 5th international conference on Supercomputing table of contents
Cologne, West Germany
Pages: 274 - 283  
Year of Publication: 1991
ISBN:0-89791-434-1
Authors
David J. Lilja  Center for Supercomputing Research and Development, University of Illinois at Urbana-Champaign, Urbana, Illinois
Pen-Chung Yew  Center for Supercomputing Research and Development, University of Illinois at Urbana-Champaign, Urbana, Illinois
Sponsor
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 15,   Citation Count: 7
Additional Information:

references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/109025.109093
What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
2
3
 
4
M. Berry. "The Perfect Club Benchmarks: Effective Performance Evaluation of Supercomputers", Univ. of Illinois CSRD Rpt. No. 827, May 1989.
 
5
L. M. Censier and P. Feautrler. "A New Solution to Coherence Problems in Multlcache Systems," IEEE Tran. on Computers, Dec. 1978, pp. 1112- 1118.
6
 
7
H. Cheong and A. V. Veidenbaum. "Stale Data Detection and Coherence Enforcement Using Flow Analysis," Int. Conf. Par. Proe., Vol. I, 1988, pp. 138-145.
8
 
9
R. Eigenmann, et al. "Cedar Fortran and Its Compiler", Univ. of Illinois CSRD Rpt. No. 966, Jan. 1990.
10
11
 
12
A. Gupta, et al. "Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes," Int. Conf. Par. Proc., Vol. I, 1990, pp. 312-321.
 
13
14
 
15
C. P. Kruskal and M. Snir. "The Performance of Multistage Interconnection Networks for Multiprocessors," IEEE Tran. on Computers, Dec. 1983, pp. 1091-1098.
 
16
D. J. Kuck, et al. "Parallel Supercomputing Today and the Cedar Approach," Science, 28 Feb. 1986, pp. 967-974.
 
17
D. J. Lilja and P.-C. Yew. "A Compiler-Assisted Directory-Based Cache Coherence Scheme", Univ. of Illinois, CSRD Rpt. No. 990, Nov. 1990.
18
 
19
S. L. Min and J.-L. Baer. ~'A Timestamp-based Cache Coherence Scheme," Int. Conf. Par. Pro~., Vol. I, 1989, pp. 23-32.
20
21
 
22
G. F. Pfister, et al. "The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture," Int. Conf. Par. Proc., 1985, pp. 764-771.
23


Collaborative Colleagues:
David J. Lilja: colleagues
Pen-Chung Yew: colleagues