Accurate modelling of interconnection networks in vector supercomputers

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Accurate modelling of interconnection networks in vector supercomputers

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International Conference on Supercomputing archive
Proceedings of the 5th international conference on Supercomputing table of contents

Cologne, West Germany

Pages: 264 - 273

Year of Publication: 1991

ISBN:0-89791-434-1

Authors

J. E. Smith	Cray Research, Inc., Chippewa Falls, WI
W. R. Taylor	Cray Research, Inc., Chippewa Falls, WI

Sponsor

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 16, Citation Count: 10

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	L. Rodney Goke , G. J. Lipovski, Banyan networks for partitioning multiprocessor systems, Proceedings of the 1st annual symposium on Computer architecture, p.21-28, December 09-11, 1973
	2	D.H. Lawrie, "Access and Alignment of Data in an Array Processor," IEEE Transactions on Computers, vol. C-24, pp. 1145-1155, December 1975.
	3	J.H. Patel, "Performance of Processor-Memory Interconnections for Multiprocessors," IEEE Transactions on Computers, vol. c-30, pp. 771- 780, October 1981.
	4	D.M. Dias and J. R. Jump, "Analysis and Simulation of Buffered Delta Networks," IEEE Transactions on Computers, vol. C-30, pp. 273- 282, April 1981.
	5	C.P. Kruskal and M. Snir, "The Performance of Multistage Interconnection Networks for Multiprocessors,' ' IEEE Transactions on Computers, vol. C-32, pp. 1091-1098, December 1983.
	6	M. Kumar and J. R. Jump, "Performance Enhancement in Buffered Delta Networks Using Crossbar Switches and Multiple Links," Journal of Parallel and Distributed Computing, vol. 1, pp. 81-103, 1984.
	7	E.D. Brooks III, "The Indirect k-ary n-cube for a Vector Processing Environment," Parallel Computing, vol. 6, pp. 339-348, 1988.
	8	K.E. Batcher, "The Flip Network in Staran," Proc. of the 1976 International Conference on Parallel Processing, pp. 65-71, August 1976.
	9	G. Ptister, W. Brantley, D. George, S. Harvey, W. Kleinfelder, K. McAuliffe, E. Melton, V. Norton, and J. Weiss, "The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture," Proc. 1985 International Conference on Parallel Processing, pp. 764-771, Aug. 1985.
	10	G. Schmidt, "The Butterfly Parallel Processor," Proc. 2nd Int. Conf. on Supercomputing, pp. 362-365, 1987.
	11	Tomas Lang , Lance Kurisaki, Nonuniform traffic spots (NUTS) in multistage interconnection networks, Journal of Parallel and Distributed Computing, v.10 n.1, p.55-67, Sep. 1990 [doi>10.1016/0743-7315(90)90006-B]
	12	D. T. Harper, III, Block, Multistride Vector, and FFT Accesses in Parallel Memory Systems, IEEE Transactions on Parallel and Distributed Systems, v.2 n.1, p.43-51, January 1991 [doi>10.1109/71.80188]

CITED BY 10

	Josep Torrellas , Zheng Zhang, The performance of the Cedar multistage switching network, Proceedings of the 1994 conference on Supercomputing, p.265-274, December 1994, Washington, D.C., United States
	Montse Peiron , Mateo Valero , Eduard Ayguadé, Synchronized access to streams in SIMD vector multiprocessors, Proceedings of the 8th international conference on Supercomputing, p.23-32, July 11-15, 1994, Manchester, England
	J. E. Smith , W. R. Taylor, Characterizing memory performance in vector multiprocessors, Proceedings of the 6th international conference on Supercomputing, p.35-44, July 19-24, 1992, Washington, D. C., United States
	Montse Peiron , Mateo Valero , Eduard Ayguadé , Tomás Lang, Vector multiprocessors with arbitrated memory access, ACM SIGARCH Computer Architecture News, v.23 n.2, p.243-252, May 1995
	Josep Torrellas , Zheng Zhang, The performance of the cedar multistage switching network, Proceedings of the 1994 ACM/IEEE conference on Supercomputing, November 14-18, 1994, Washington, D.C.
	Steven Robbins , Kay A. Robbins, Buffered Banks in Multiprocessor Systems, IEEE Transactions on Computers, v.44 n.4, p.518-530, April 1995
	Guy E. Blelloch , Phillip B. Gibbons , Yossi Matias , Marco Zagha, Accounting for memory bank contention and delay in high-bandwidth multiprocessors, Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures, p.84-94, June 24-26, 1995, Santa Barbara, California, United States
	Josep Torrellas , Zheng Zhang, The Performance of the Cedar Multistage Switching Network, IEEE Transactions on Parallel and Distributed Systems, v.8 n.4, p.321-336, April 1997
	Guy E. Blelloch , Phillip B. Gibbons , Yossi Matias , Marco Zagha, Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors, IEEE Transactions on Parallel and Distributed Systems, v.8 n.9, p.943-958, September 1997
	A. M. del Corral , J. M. Llaberia, Minimizing Conflicts Between Vector Streams in Interleaved Memory Systems, IEEE Transactions on Computers, v.48 n.4, p.449-456, April 1999