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Hardware support for code integrity in embedded processors
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Source International Conference on Compilers, Architecture and Synthesis for Embedded Systems archive
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems table of contents
San Francisco, California, USA
SESSION: Security table of contents
Pages: 55 - 65  
Year of Publication: 2005
ISBN:1-59593-149-X
Authors
Milena Milenković  IBM, Austin, TX
Aleksandar Milenković  The University of Alabama in Huntsville, Huntsville, AL
Emil Jovanov  The University of Alabama in Huntsville, Huntsville, AL
Sponsors
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
ACM  New York, NY, USA
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ABSTRACT

Computer security becomes increasingly important with continual growth of the number of interconnected computing platforms. Moreover, as capabilities of embedded processors increase, the applications running on these systems also grow in size and complexity, and so does the number of security vulnerabilities. Attacks that impair code integrity by injecting and executing malicious code are one of the major security issues. This problem can be addressed at different levels, from more secure software and operating systems, down to solutions that require hardware support. Most of the existing techniques tackle the problem of security flaws at the software level, but this approach lacks generality and often induces prohibitive overhead in performance and cost, or generates a significant number of false alarms. On the other hand, a further increase in the number of transistors on a single chip enables integrated hardware support for functions that formerly were restricted to the software domain. Hardware-supported defense techniques have the potential to be more general and more efficient than solely software solutions. This paper proposes four new architectural extensions to ensure complete run-time code integrity using instruction block signature verification. The experimental analysis shows that the proposed techniques have low performance and energy overhead. In addition, the proposed mechanism has low hardware complexity, and does not impose either changes to the compiler or changes to the existing instruction set architecture.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Milena Milenković: colleagues
Aleksandar Milenković: colleagues
Emil Jovanov: colleagues