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A unified HW/SW interface model to remove discontinuities between HW and SW design
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Source International Conference On Embedded Software archive
Proceedings of the 5th ACM international conference on Embedded software table of contents
Jersey City, NJ, USA
SESSION: Design methodologies table of contents
Pages: 159 - 163  
Year of Publication: 2005
ISBN:1-59593-091-4
Authors
Aimen Bouchhima  TIMA Laboratory, CEDEX, France
Xi Chen  TIMA Laboratory, CEDEX, France
Frédéric Pétrot  TIMA Laboratory, CEDEX, France
Wander O. Cesário  TIMA Laboratory, CEDEX, France
Ahmed A. Jerraya  TIMA Laboratory, CEDEX, France
Sponsors
SIGBED: ACM Special Interest Group on Embedded Systems
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 1,   Downloads (12 Months): 28,   Citation Count: 2
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ABSTRACT

One major challenge in System-on-Chip (SoC) design is the definition and design of interfaces between hardware and software. Traditional ASIC designer and software designer model HW/SW interface twice. Using two separate models introduces a discontinuity between hardware and software. This paper introduces a unified HW/SW component model to describe different parts of HW/SW interface at different abstraction levels. The benefits of using the proposed model are two fold: first, it provides a single model to present system design from abstract specification to mixed HW/SW implementation and second, it enables full system simulation at different abstraction level during refinement flow.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
A. A. Jerraya, W. Wolf, << Multiprocessor Systems-on-Chips >>, Morgan Kaufmann Publishers, ISBN 0-12-385251-X, September 2004.
 
2
A. Sangiovanni Vincentelli, <<Platform-based Design>>, EEDesign of EETimes, February 2002.
 
3
K. Keutzer, A. Newton, J. Rabaey, and A. Sangiovanni-Vincentelli. System-level design: orthogonalization of concerns and platform-based de-sign. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
 
4
Keutzer, K., Malik, S., Newton, A. R., System Level Design: Orthogonolization of Concerns and Platform-Based Design, IEEE Trans. Computer-Aided Design of Integrated Circuit and Systems, vol.19, no. 12, Dec.2000.
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M.Zitterbart, "A Model for Flexible High performance Communication Subsystems", IEEE Journal on selected areas in communication, VOL. 11, NO, 4, MAY 1993.
 
7
G. De Micheli, R.K. Gupta, Hardware-Software Codesign, Proceedings of the IEEE, V85, No3, 1997.
 
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Collaborative Colleagues:
Aimen Bouchhima: colleagues
Xi Chen: colleagues
Frédéric Pétrot: colleagues
Wander O. Cesário: colleagues
Ahmed A. Jerraya: colleagues