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Exploiting last idle periods of links for network power management
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Source International Conference On Embedded Software archive
Proceedings of the 5th ACM international conference on Embedded software table of contents
Jersey City, NJ, USA
SESSION: Optimization table of contents
Pages: 134 - 137  
Year of Publication: 2005
ISBN:1-59593-091-4
Authors
F. Li  Pennsylvania State University, University Park, PA
G. Chen  Pennsylvania State University, University Park, PA
M. Kandemir  Pennsylvania State University, University Park, PA
M. Karakoy  Imperial College, London, UK
Sponsors
SIGBED: ACM Special Interest Group on Embedded Systems
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

Network power optimization is becoming increasingly important as the sizes of the data manipulated by parallel applications and the complexity of inter-processor data communications are continuously increasing. Several hardware-based schemes have been proposed in the past for reducing network power consumption, either by turning off unused communication links or by lowering voltage/frequency in links with low usage. While the prior research shows that these schemes can be effective in certain cases, they share the common drawback of not being able to predict the link active and idle times very accurately. This paper, instead, proposes a compiler-based scheme that determines the last use of communication links at each loop nest and inserts explicit link turn-off calls in the application source. Specifically, for each loop nest, the compiler inserts a turn-off call per communication link. Each turned-off link is reactivated upon the next access to it. We automated this approach within a parallelizing compiler and applied it to eight array-intensive embedded applications.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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J. Kim and M. Horowitz. Adaptive supply serial links with sub-1V operation and per-pin clock recovery. In Proc. International Solid-State Circuits Conference, Feb. 2002.
 
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Collaborative Colleagues:
F. Li: colleagues
G. Chen: colleagues
M. Kandemir: colleagues
M. Karakoy: colleagues