Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor

ABSTRACT

The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the main tasks in the design flow, aiming to certify the system functionality has been accomplished accordingly to the specification. A simulation based technique known as functional verification has been followed by the industry. In recent years, several articles in functional verification have been presented, focusing either on specific design verification experiments or on methods to improve and accelerate coverage reaching. In the first category, the majority of the papers are aimed to processors verification, while communication systems experiences were not such commonly reported. In the second category, different authors have proposed methodologies, which need an extensive and complex work by the verification engineer on tuning the acceleration algorithms to the specific design. In the present paper, we present a functional verification methodology applied to a Bluetooth Baseband adaptor core, described in SystemC RTL. Two techniques are considered, one following the traditional framework of applying random stimuli and checking functional coverage aspects; in the second one, a simple acceleration procedure, based on redundant stimuli filtering, is included. For both solutions, a hierarchical approach is adopted. We present several results comparing both solutions, showing the gain obtained in using the acceleration technique. Additionally, we show how results on a real testbench application environment correlate to the hierarchical verification approach taken.

REFERENCES

• 1: Silicon Industry Association, Silicon Technology Roadmap for Semiconductors, 2001.
• 2: Janick Bergeron, Writing Testbenches: Functional Verification of HDL Models, Second Edition, Kluwer Academic Publishers, Norwell, MA, 2003
• 3: S. Rosenberg, Combined Coverage Verification Speeds Verification. EEdesign, 2003.
• 4: M. Bose, J.Shin, and E. Rudnick, A Genetic Approach to Automatic Bias Generation for Biased Random Instruction Generation. Evolutionary Congress Proc on, pp 442--448, 2001.
• 5: M. Braun , W. Rosenstiel , K.-D. Schubert, Comparison of Bayesian networks and data mining for coverage directed verification category simulation-based verification, Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop, p.91, November 12-14, 2003
• 6: Karina R. G. da Silva , Elmar U. K. Melcher , Guido Araujo , Valdiney Alves Pimenta, An automatic testbench generation tool for a SystemC functional verification methodology, Proceedings of the 17th symposium on Integrated circuits and system design, September 07-11, 2004, Pernambuco, Brazil [doi>10.1145/1016568.1016592]
• 7: Z.Gu, Z. Yu, and Q.Zhang, Functional Verification Methodology of a 32-bit RISC Microprocessor. IEEE international conference on circuits and systems, pp 1454--1457, 2002.
• 8: Yves Mathys , André Châtelain, Verification strategy for integration 3G baseband SoC, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775835]
• 9: V. Fernandez, L. Berrojo, and A. Jalon, Design, Functional Verification and Test of a MPEG2-TS Multiplexer for an On-Board Satellite Processor. Proceedings of the XVII Conference on Design of Circuits and Integrated Systems (DCIS2002). 2002.
• 10: Serdar Tasiran , Kurt Keutzer, Coverage Metrics for Functional Validation of Hardware Designs, IEEE Design & Test, v.18 n.4, p.36-45, July 2001 [doi>10.1109/54.936247]
• 11: A. Hekmatmpour, and J. Coulter, Coverage-Directed Management and Optimization of Random Functional Verification. Proceedings International Test Conference, vol 1, pp 148--155, 2003.
• 12: Bluetooth Specification, version 1.1 , 2001. www.bluetooth.org <http://www.bluetooth.org> (at March 2005).

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Optimization

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Verification; Simulation

General Terms:
Design, Experimentation, Reliability, Verification

Keywords:
coverage analysis, functional verification, hierarchical verification, optimization, verification strategy