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An automated exploration framework for FPGA-based soft multiprocessor systems
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Source International Conference on Hardware Software Codesign archive
Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis table of contents
Jersey City, NJ, USA
SESSION: Algorithms and methodologies for new architectures table of contents
Pages: 273 - 278  
Year of Publication: 2005
ISBN:1-59593-161-9
Authors
Yujia Jin  University of California at Berkeley, CA
Nadathur Satish  University of California at Berkeley, CA
Kaushik Ravindran  University of California at Berkeley, CA
Kurt Keutzer  University of California at Berkeley, CA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
SIGBED: ACM Special Interest Group on Embedded Systems
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 5,   Downloads (12 Months): 38,   Citation Count: 9
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ABSTRACT

FPGA-based soft multiprocessors are viable system solutions for high performance applications. They provide a software abstraction to enable quick implementations on the FPGA. The multiprocessor can be customized for a target application to achieve high performance. Modern FPGAs provide the capacity to build a variety of micro-architectures composed of 20-50 processors, complex memory hierarchies, heterogeneous interconnection schemes and custom co-processors for performance critical operations. However, the diversity in the architectural design space makes it difficult to realize the performance potential of these systems. In this paper we develop an exploration framework to build efficient FPGA multiprocessors for a target application. Our main contribution is a tool based on Integer Linear Programming to explore micro-architectures and allocate application tasks to maximize throughput. Using this tool, we implement a soft multiprocessor for IPv4 packet forwarding that achieves a throughput of 2 Gbps, surpassing the performance of a carefully tuned hand design.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
EEMBC. http://www.eembc.org/.
 
2
ILOG CPLEX. http://www.ilog.com/products/cplex/.
 
3
A. Atamtürk and M. W. Savelsbergh. Integer Programming Software Systems. Technical Report BCOL.03.01, IEOR, University of California at Berkeley, January 2003.
 
4
Chris Rowen, Tensilica Inc. Fundamental Change in MPSoCs: A fifteen year outlook. In MPSOC'03 Workshop Proceedings. International Seminar on Application-Specific Multi-Processor SoC, 2003.
5
 
6
M. Gries and Y. Jin. Comprehensively Exploring the Design Space. In M. Gries and K. Keutzer, editors, Building ASIPs: The MESCAL Methodology, pages 131--178. Springer Inc., 2005.
 
7
M. Gries and K. Keutzer, editors. Building ASIPs: The MESCAL Methodology. Springer Inc., 2005.
 
8
P. D. Hoang and J. M. Rabaey. Scheduling of DSP Programs onto Multiprocessors for Maximum Throughput. In IEEE Transactions on Signal Processing, volume 41, pages 2225--2235, June 1993.
 
9
K. Ravindran, N. Satish, Y. Jin, and K. Keutzer. An FPGA-based Soft Multiprocessor System for IPv4 Packet Forwarding. In International Conference on Field Programmable Logic and Applications (FPL), August 2005.
 
10
M. Ruiz-Sánchez, E. Biersack, and W. Dabbous. Survey and Taxonomy of IP Address Lookup Algorithms. Network, IEEE, Vol.15, Iss.2, pages 8--23, March-April 2001.
 
11
Xilinx, Inc. Embedded Systems Tools Guide, Xilinx Embedded Development Kit, EDK version 6.2i edition, June 2004.

CITED BY  9

Collaborative Colleagues:
Yujia Jin: colleagues
Nadathur Satish: colleagues
Kaushik Ravindran: colleagues
Kurt Keutzer: colleagues