| Satisfying real-time constraints with custom instructions |
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International Conference on Hardware Software Codesign
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Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
table of contents
Jersey City, NJ, USA
SESSION: Accelerating applications through customized instruction sets
table of contents
Pages: 166 - 171
Year of Publication: 2005
ISBN:1-59593-161-9
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Authors
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Pan Yu
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National University of Singapore, Republic of Singapore
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Tulika Mitra
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National University of Singapore, Republic of Singapore
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| Bibliometrics |
Downloads (6 Weeks): 7, Downloads (12 Months): 35, Citation Count: 2
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ABSTRACT
Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application of instruction-set extensions to meet timing constraints in real-time embedded systems. In order to satisfy real-time constraints, the worst-case execution time (WCET) of a task should be reduced as opposed to its average-case execution time. Unfortunately, existing custom instruction selection techniques based on average-case profile information may not reduce a task's WCET. We first develop an Integer Linear Programming (ILP) formulation to choose optimal instruction-set extensions for reducing the WCET. However, ILP solutions for this problem are often too expensive to compute. Therefore, we also propose an efficient and scalable heuristic that obtains quite close to the optimal results. Experiment results indicate that suitable choice of custom instructions can reduce the WCET of our benchmark programs by as much as 42% (23.5% on an average).
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Altera. Nios embedded processor, 2003.
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3
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4
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6
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Jason Cong , Yiping Fan , Guoling Han , Zhiru Zhang, Application-specific instruction generation for configurable processor architectures, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
[doi> 10.1145/968280.968307]
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8
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Paolo Faraboschi , Geoffrey Brown , Joseph A. Fisher , Giuseppe Desoli , Fred Homewood, Lx: a technology platform for customizable VLIW embedded processing, Proceedings of the 27th annual international symposium on Computer architecture, p.203-213, June 2000, Vancouver, British Columbia, Canada
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9
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10
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M. R. Guthaus et al. Mibench: A free, commercially representative embedded benchmark suite. In IEEE Annual Workshop on Workload Characterization, 2001.
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11
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12
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Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States
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13
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14
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S. Lee et al. A flexible tradeoff between code size and WCET using a dual instruction set processor. In SCOPES, 2004.
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15
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16
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17
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F. Stappert. WCET benchmarks. Available from http://www.c-lab.de/home/en/download.html.
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18
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Stretch. S5000 software-configurable processors, 2004.
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19
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F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha. Custom-instruction synthesis for extensible-processor platforms. IEEE TCAD, 23(2), 2004.
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20
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21
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22
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W. Zhao et al. Tuning the WCET of embedded applications. In RTAS, 2004.
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23
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