Energy conscious online architecture adaptation for varying latency constraints in sensor network applications

ABSTRACT

Sensor network applications face continuously changing environments, which impose varying processing loads on the sensor node. This paper presents an online control method which adapts the architecture to minimize energy consumption while satisfying varying latency constraints. The method predicts processing load requirements over a finite time window and accordingly adapts the architecture. The behaviour of the hardware modules over time has been approximated with a Continuous Time Markov Process. Adaptive image processing for vehicle tracking was used as a case study for this approach.

REFERENCES

• 1: Luca Benini , Alessandro Bogliolo , Giovanni De Micheli, A survey of design techniques for system-level dynamic power management, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.8 n.3, p.299-316, June 2000 [doi>10.1109/92.845896]
• 2: C. G. Cassandras and S. LaFortune. Introduction to Discrete Event Systems. Kluwer Academic Publishers, 1999.
• 3: P. Eles, Z. Peng, K. Kuchinski, and A. Doboli. System Level Hardware/Software Partitioning using Simulated Annealing and Tabu Search. Kluwer Academic Publishers, 1997.
• 4: E. Feinberg. Optimal control of average reward constrained continuous time finite markov decision processes. Proceedings of the IEEE Conference on Decision and Control, pages 3805--3810, 2002.
• 5: S. Hauck , T. W. Fry , M. M. Hosler , J. P. Kao, The Chimaera reconfigurable functional unit, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.87, April 16-18, 1997
• 6: S. Kallakuri, A. Doboli, and S. Doboli. Stochastic modeling based environment for synthesis and comparison of bus arbitration policies. Proceedings of IEEE Annual Symposium on VLSI, pages 199--206, 2004.
• 7: Jawad Khan , Ranga Vemuri, An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms, Proceedings of the conference on Design, Automation and Test in Europe, p.622-627, March 07-11, 2005 [doi>10.1109/DATE.2005.62]
• 8: Averill M. Law , W. David Kelton, Simulation Modeling and Analysis, McGraw-Hill Higher Education, 1997
• 9: Roman Lysecky , Frank Vahid, A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning, Proceedings of the conference on Design, Automation and Test in Europe, p.18-23, March 07-11, 2005 [doi>10.1109/DATE.2005.38]
• 10: Alan Mainwaring , David Culler , Joseph Polastre , Robert Szewczyk , John Anderson, Wireless sensor networks for habitat monitoring, Proceedings of the 1st ACM international workshop on Wireless sensor networks and applications, September 28-28, 2002, Atlanta, Georgia, USA [doi>10.1145/570738.570751]
• 11: Benoit Miramond , Jean-Marc Delosme, Design Space Exploration for Dynamically Reconfigurable Architectures, Proceedings of the conference on Design, Automation and Test in Europe, p.366-371, March 07-11, 2005 [doi>10.1109/DATE.2005.118]
• 12: Q. Qiu, Q.Wu, and M.Pedram. Stochastic modeling of a power-managed system: Construction and optimisation. IEEE Transactions on Computer Aided Design, 20(9):1200--1217, October 2001.
• 13: M. Rahimi, R. Pon, W. Kaiser, G. Sukhatme, D. Estrin, and M. Srivastava. Adaptive sampling for environmental robots. Proc. of International Conference on Robotics and Automation, 2004.
• 14: Greg Stitt , Frank Vahid, Hardware/software partitioning of software binaries, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.164-170, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774596]
• 15: Greg Stitt , Roman Lysecky , Frank Vahid, Dynamic hardware/software partitioning: a first approach, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775896]
• 16: M. Writhlin and H. B. Disc: The dynamic instruction set computer. fpgas for fast board developement and reconfigurable computing. Proceedings of the SPIE 2607, pages 92--103, 1995.
• 17: Smart Sensor Architecture Customized for Image Processing Applications, Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'04), p.396, May 25-28, 2004

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.4 VLSI Systems

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Adaptable architectures

General Terms:
Design

Keywords:
continuous time adaptation, sensor networks