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Key research problems in NoC design: a holistic perspective
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Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis table of contents
Jersey City, NJ, USA
SESSION: Network-on-chip architectures table of contents
Pages: 69 - 74  
Year of Publication: 2005
ISBN:1-59593-161-9
Authors
Umit Y. Ogras  Carnegie Mellon University, Pittsburgh, PA
Jingcao Hu  Carnegie Mellon University, Pittsburgh, PA
Radu Marculescu  Carnegie Mellon University, Pittsburgh, PA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
SIGBED: ACM Special Interest Group on Embedded Systems
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 25,   Downloads (12 Months): 173,   Citation Count: 22
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ABSTRACT

Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex on-chip communication problems. The lack of an unified representation of applications and architectures makes NoC problem formulation and classification both difficult and obscure. To remedy this situation, we provide a general description for NoC architectures and applications and then enumerate several outstanding research problems (denoted by P1-P8) organized under three topics: communication infrastructure synthesis, communication paradigm selection, and application mapping optimization. Far from being exhaustive, the discussed problems are deemed essential for future NoC research.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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S. Kumar, et. al. Network on a chip: An architecture for billion transistor era. In Proc. IEEE NorChip Conf, 2000.
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J. Hu, R. Marculescu. Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans. on CAD of Integrated Circuits and Systems, 24(4), April 2005.
 
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M. Pirretti et. al. Fault tolerant algorithms for Network-On-Chip interconnect. In Proc. IEEE Symp. on VLSI, February 2004
 
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I. Saastamoinen, et. al. Buffer implementation for Proteo Network-on-Chip. In Proc. Intl. Symp. on Circuits and Systems, 2003.
 
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J. Dielissen, et. al. Concepts and implementation of the Philips Network-on-Chip. IP-based SoC Design, Nov. 2003.
 
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K. Lee, et. al. A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform. Intl. Solid-State Circuits Conf., 2004.
 
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L. P. Carloni, et. al. Theory of latency-insensitive design. IEEE Trans. on CAD of Integrated Circuits and Systems, 20(9), Sept. 2001.
 
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T. T. Ye, G. De Micheli. Physical planning for multiprocessor networks and switch fabrics. In Proc. ASAP, 2003.
 
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A. Morgenshtein, et. al. Comparative analysis of serial vs. parallel links in networks on chip. Intl. Symp. on System-on-Chip 2004.

CITED BY  22

Collaborative Colleagues:
Umit Y. Ogras: colleagues
Jingcao Hu: colleagues
Radu Marculescu: colleagues