| Key research problems in NoC design: a holistic perspective |
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International Conference on Hardware Software Codesign
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Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
table of contents
Jersey City, NJ, USA
SESSION: Network-on-chip architectures
table of contents
Pages: 69 - 74
Year of Publication: 2005
ISBN:1-59593-161-9
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Downloads (6 Weeks): 25, Downloads (12 Months): 173, Citation Count: 22
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ABSTRACT
Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex on-chip communication problems. The lack of an unified representation of applications and architectures makes NoC problem formulation and classification both difficult and obscure. To remedy this situation, we provide a general description for NoC architectures and applications and then enumerate several outstanding research problems (denoted by P1-P8) organized under three topics: communication infrastructure synthesis, communication paradigm selection, and application mapping optimization. Far from being exhaustive, the discussed problems are deemed essential for future NoC research.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 22
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Hyung Gyu Lee , Naehyuck Chang , Umit Y. Ogras , Radu Marculescu, On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.3, p.1-20, August 2007
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Xianfang Tan , Lei Zhang , Shankar Neelkrishnan , Mei Yang , Yingtao Jiang , Yulu Yang, Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
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Jun Wang , Hongbo Zeng , Kun Huang , Ge Zhang , Yan Tang, Zero-efficient buffer design for reliable network-on-chip in tiled chip-multi-processor, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
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Maurizio Palesi , Giuseppe Longo , Salvatore Signorino , Rickard Holsmark , Shashi Kumar , Vincenzo Catania, Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, p.97-106, April 07-10, 2008
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Cristian Grecu , Andre Ivanov , Partha Pande , Axel Jantsch , Erno Salminen , Umit Ogras , Radu Marculescu, Towards Open Network-on-Chip Benchmarks, Proceedings of the First International Symposium on Networks-on-Chip, p.205, May 07-09, 2007
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