Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture

ABSTRACT

This paper presents a method of on-chip communication topology synthesis and optimization for a shared multi-bus based architecture. An assumption for the synthesis is that the system has already been partitioned and mapped onto the appropriate components of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. We model the communication behavior of each module as a set of communication lifetime intervals (CLTIs), which are optimized in terms of number of overlaps among them, size of bus width and the minimum number of buses, using ILP (integer linear programming) formulation. We synthesize the communication topology and further optimize the architecture based on the intermodule communication statistics, which are obtained from the system level profiling of an application. The result of applying this approach to the Talking Assistant used in ubiquitous computing application demonstrates the utility of our techniques to synthesize the communication architecture for a complex system.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

Additional Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

General Terms:
Algorithms, Design

Keywords:
algorithms, on-chip communication architecture synthesis, optimization