| Traffic generation and performance evaluation for mesh-based NoCs |
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SBCCI
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Proceedings of the 18th annual symposium on Integrated circuits and system design
table of contents
Florianolpolis, Brazil
SESSION: Networks-on-chip
table of contents
Pages: 184 - 189
Year of Publication: 2005
ISBN:1-59593-174-0
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Authors
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Leonel Tedesco
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Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Porto Alegre, RS, Brazil
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Aline Mello
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Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Porto Alegre, RS, Brazil
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Diego Garibotti
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Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Porto Alegre, RS, Brazil
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Ney Calazans
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Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Porto Alegre, RS, Brazil
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Fernando Moraes
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Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Porto Alegre, RS, Brazil
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Downloads (6 Weeks): 9, Downloads (12 Months): 42, Citation Count: 3
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ABSTRACT
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these methods have to address are the generation and evaluation of network traffic. Traffic generation allows injecting packets in the network according to application constraint specifications such as transmission rate and end-to-end latency. Performance evaluation helps in computing latency and throughput at network channels/interfaces, as well as to identify congestion and hot-spots. This paper reviews related works in traffic generation and performance evaluation for mesh topology NoCs, and proposes general methods for both aspects. Three parameters are used here to define traffic generation: packet spatial distribution, packet injection rate and packet size. Two types of methods to evaluate performance in NoCs are discussed: (i) external evaluation, a common strategy found in related works, where the network is considered as a black box and traffic results are obtained only from the external network interfaces; (ii) internal evaluation, where performance is computed in each network channel. The paper presents the result of experiments conducted in an 8x8 mesh network, varying the routing algorithms and the number of virtual channels. The main contribution of this work is the set of methods for internal NoC evaluation, which help designers to optimize the network under different traffic scenarios.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Adrijean Adriahantenaina , Herve Charlery , Alain Greiner , Laurent Mortiez , Cesar Albenes Zeferino, SPIN: A Scalable, Packet Switched, On-Chip Micro-Network, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20070, March 03-07, 2003
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Fernando Moraes , Ney Calazans , Aline Mello , Leandro Möller , Luciano Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, v.38 n.1, p.69-93, October 2004
[doi> 10.1016/j.vlsi.2004.03.003]
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CITED BY 3
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Gianluca Palermo , Giovanni Mariani , Cristina Silvano , Riccardo Locatelli , Marcello Coppola, A topology design customization approach for STNoC, Proceedings of the 2nd international conference on Nano-Networks, September 24-26, 2007, Catania, Italy
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Leonel Tedesco , Aline Mello , Leonardo Giacomet , Ney Calazans , Fernando Moraes, Application driven traffic modeling for NoCs, Proceedings of the 19th annual symposium on Integrated circuits and systems design, August 28-September 01, 2006, Ouro Preto, MG, Brazil
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