| Virtual channels in networks on chip: implementation and evaluation on hermes NoC |
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SBCCI
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Proceedings of the 18th annual symposium on Integrated circuits and system design
table of contents
Florianolpolis, Brazil
SESSION: Networks-on-chip
table of contents
Pages: 178 - 183
Year of Publication: 2005
ISBN:1-59593-174-0
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Authors
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Aline Mello
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Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Porto Alegre, RS, BRASIL
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Leonel Tedesco
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Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Porto Alegre, RS, BRASIL
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Ney Calazans
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Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Porto Alegre, RS, BRASIL
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Fernando Moraes
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Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Porto Alegre, RS, BRASIL
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Downloads (6 Weeks): 30, Downloads (12 Months): 126, Citation Count: 4
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ABSTRACT
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congestion in NoCs reduces the overall system performance. This effect is particularly strong in networks where a single buffer is associated with each input channel, which simplifies router design, but prevents packets from sharing a physical channel at any given instant of time. The goal of this work is to describe the implementation of a mechanism to reduce performance penalization due to packet concurrence for network resources in NoCs. One way to reduce congestion is to multiplex a physical channel using virtual channels (VCs). VCs reduce latency and increase network throughput. The insertion of VCs also enables to implement policies for allocating the physical channel bandwidth, which enables to support quality of service (QoS) in applications. This paper has two main contributions. The first is the detailed implementation of a NoC router with a parameterizable number of VCs. The second is the evaluation of latency and throughput in reasonably sized instances of the Hermes NoC (8x8 mesh), with and without VCs. Additionally, the paper compares the features of the proposed router with others employing VCs. Results show that NoCs with VCs accept higher injections rates w.r.t. NoCs without VCs, with a small standard deviation in the latency values, guaranteeing precise packet latency estimation.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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International Sematech. "International Technology Roadmap for Semiconductors - 2002" Update, 2002. Available at http://public.itrs.net.
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Martin, G.; Chang, H. "System on Chip Design". In: 9th International Symposium on Integrated Circuits, Devices & Systems, Tutorial 2, 2001.
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Rijpkema, E.; et al. "A Router Architecture for Networks on Silicon". In: PROGRESS'2001.
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Théodore Marescaux , Andrei Bartic , Diederik Verkest , Serge Vernalde , Rudy Lauwereins, Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs, Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications, p.795-805, September 02-04, 2002
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Kees Goossens , John Dielissen , Jef van Meerbergen , Peter Poplavko , Andrei Rădulescu , Edwin Rijpkema , Erwin Waterlander , Paul Wielage, Guaranteeing the quality of services in networks on chip, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
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Kavaldjiev, N.; Smit, G.; Jansen, P. "Two Architectures for On-chip Virtual Channel Router". PROGRESS, 2004, pp. 96--102.
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Bertozzi, D.; Benini, L. "Xpipes: A Network-on-chip Architecture for Gigascale Systems-on-Chip". IEEE Circuits and Systems Magazine, 4(2), 2004, pp. 18--31.
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Chuang, S.-T.; Goel, A.; Mckeown, N.; Prabhakar, B. "Matching output queuing with a combined input output queued switch". IEEE Journal on Selected Areas in Communications, 17(6), 1999, pp.1030--1039.
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Fernando Moraes , Ney Calazans , Aline Mello , Leandro Möller , Luciano Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, v.38 n.1, p.69-93, October 2004
[doi> 10.1016/j.vlsi.2004.03.003]
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INDEX TERMS
Primary Classification:
B.
Hardware
B.4
INPUT/OUTPUT AND DATA COMMUNICATIONS
B.4.3
Interconnections (subsystems)
Subjects:
Asynchronous/synchronous operation
Additional Classification:
B.
Hardware
B.4
INPUT/OUTPUT AND DATA COMMUNICATIONS
B.4.3
Interconnections (subsystems)
Subjects:
Fiber optics;
Interfaces;
Parallel I/O;
Topology (e.g., bus, point-to-point);
Physical structures (e.g., backplanes, cables, chip carriers)
General Terms:
Design,
Experimentation,
Measurement,
Performance
Keywords:
network-on-chip,
performance,
virtual channel
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