ACM Home Page
Please provide us with feedback. Feedback
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
Full text PdfPdf (288 KB)
Source SBCCI archive
Proceedings of the 18th annual symposium on Integrated circuits and system design table of contents
Florianolpolis, Brazil
SESSION: Networks-on-chip table of contents
Pages: 178 - 183  
Year of Publication: 2005
ISBN:1-59593-174-0
Authors
Aline Mello  Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Porto Alegre, RS, BRASIL
Leonel Tedesco  Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Porto Alegre, RS, BRASIL
Ney Calazans  Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Porto Alegre, RS, BRASIL
Fernando Moraes  Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Porto Alegre, RS, BRASIL
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 30,   Downloads (12 Months): 126,   Citation Count: 4
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1081081.1081128
What is a DOI?

ABSTRACT

Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congestion in NoCs reduces the overall system performance. This effect is particularly strong in networks where a single buffer is associated with each input channel, which simplifies router design, but prevents packets from sharing a physical channel at any given instant of time. The goal of this work is to describe the implementation of a mechanism to reduce performance penalization due to packet concurrence for network resources in NoCs. One way to reduce congestion is to multiplex a physical channel using virtual channels (VCs). VCs reduce latency and increase network throughput. The insertion of VCs also enables to implement policies for allocating the physical channel bandwidth, which enables to support quality of service (QoS) in applications. This paper has two main contributions. The first is the detailed implementation of a NoC router with a parameterizable number of VCs. The second is the evaluation of latency and throughput in reasonably sized instances of the Hermes NoC (8x8 mesh), with and without VCs. Additionally, the paper compares the features of the proposed router with others employing VCs. Results show that NoCs with VCs accept higher injections rates w.r.t. NoCs without VCs, with a small standard deviation in the latency values, guaranteeing precise packet latency estimation.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
International Sematech. "International Technology Roadmap for Semiconductors - 2002" Update, 2002. Available at http://public.itrs.net.
 
2
Martin, G.; Chang, H. "System on Chip Design". In: 9th International Symposium on Integrated Circuits, Devices & Systems, Tutorial 2, 2001.
 
3
4
5
 
6
Rijpkema, E.; et al. "A Router Architecture for Networks on Silicon". In: PROGRESS'2001.
7
 
8
9
 
10
 
11
Kavaldjiev, N.; Smit, G.; Jansen, P. "Two Architectures for On-chip Virtual Channel Router". PROGRESS, 2004, pp. 96--102.
 
12
 
13
Bertozzi, D.; Benini, L. "Xpipes: A Network-on-chip Architecture for Gigascale Systems-on-Chip". IEEE Circuits and Systems Magazine, 4(2), 2004, pp. 18--31.
 
14
 
15
Chuang, S.-T.; Goel, A.; Mckeown, N.; Prabhakar, B. "Matching output queuing with a combined input output queued switch". IEEE Journal on Selected Areas in Communications, 17(6), 1999, pp.1030--1039.
 
16
 
17
18
 
19


Collaborative Colleagues:
Aline Mello: colleagues
Leonel Tedesco: colleagues
Ney Calazans: colleagues
Fernando Moraes: colleagues