T-shaped association of transistors: modeling of multiple channel lengths and regular associations

ABSTRACT

This work presents an analysis of a new type of composite transistor specially suited for the design of analog integrated circuits: the T-shape association of transistors. This association is composed by non-equal size unit transistors arranged in a series-parallel array with common gate, which can substitute the conventional rectangular transistors with advantages in some aspects, such as better high-frequency performance, lower output conductance and layout regularity. Dedicated tools that automatically translate the single transistors into equivalent associations without degradation in the overall circuit specifications guarantee the compatibility with the conventional analog design methodology. Some properties and applications are discussed in this paper. Experimental and simulated characteristics are shown in order to verify the behavior of the association.

REFERENCES

• 1: A. Arnaud and C. Galup-Montoro. A compact model for flicker noise in MOS transistors for analog circuit design. IEEE Transactions on Electron Devices, 50(8):1815--1818, August 2003.
• 2: A. I. A. Cunha, M. C. Schneider, and C. Galup-Montoro. An MOS transistor model for analog circuit design. IEEE Journal of Solid-State Circuits, 33(10):1510--1519, October 1998.
• 3: G. V. der Plas, J. Vandenbussche, G. Gielen, and W. Sansen. A layout synthesis methodology for array-type analog blocks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 21(6):645--661, June 2002.
• 4: P. G. Drennan and C. C. McAndrew. Understanding MOSFET mismatch for analog design. IEEE Journal of Solid-State Circuits, 38(3):450--456, March 2003.
• 5: R. Fiorelli, A. Arnaud, and C. Galup-Montoro. Series-parallel association of transistors for the reduction of random offset in non-unity gain current mirrors. In International Symposium on Circuits and Systems (ISCAS), volume 1, Vancouver, Canada, May 2004.
• 6: C. Gallup-Montoro, M. Schneider, and I. Loss. Series-parallel association of FET's for high gain and high frequency applications. IEEE Journal of Solid-State Circuits, 29(9), September 1994.
• 7: Alesssandro Girardi , Sergio Bampi, LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks, Proceedings of the conference on Design, Automation and Test in Europe, p.11106, March 03-07, 2003
• 8: D. Integration. Smash Circuit Simulator Manual. Meylan, France, 2002.
• 9: W. Maly. Computer-aided design for VLSI circuit manufacturability. Proceedings of the IEEE, 78(2):356--392, February 1990.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout; Simulation

General Terms:
Design, Measurement, Performance, Reliability

Keywords:
MOSFET, analog design, associations of transistors, modeling