A low-power crossroad switch architecture and its core placement for network-on-chip

ABSTRACT

As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication topology should possibly match communication workflows among these components. In this paper, we first propose an interconnection architecture for SoC, which uses crossroad switches to construct a dedicated communication path dynamically between any two cores. We then present a design methodology for constructing network on chip (NoC) for application-specific computer systems with profiled communication characteristics. We design a core placement tool, which automatically maps cores to a communication topology such that we can minimize the total communication energy. Experimental results show that the design methodology can generate optimized on-chip networks with fewer resources than meshes and tori, and the power saving approximates to 40%

REFERENCES

• 1: Neal K. Bambha , Shuvra S. Bhattacharyya, Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors, IEEE Transactions on Parallel and Distributed Systems, v.16 n.2, p.99-112, February 2005 [doi>10.1109/TPDS.2005.20]
• 2: A. Bellaouar,I. Abu-Khater, and M.I. Elmastry. An ultra-low-power cmos on-chip interconnect architecture. In Symposium on Low Power Electronics. Digest of Technical Papers, pages 52--53, Oct. 1995.
• 3: Davide Bertozzi , Antoine Jalabert , Srinivasan Murali , Rutuparna Tamhankar , Stergios Stergiou , Luca Benini , Giovanni De Micheli, NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip, IEEE Transactions on Parallel and Distributed Systems, v.16 n.2, p.113-129, February 2005 [doi>10.1109/TPDS.2005.22]
• 4: J. Y. Chen , W. B. Jone , J. S. Wang , H.-I. Lu , T. F. Chen, Segmented bus design for low-power systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.1, p.25-29, March 1999 [doi>10.1109/92.748197]
• 5: William J. Dally , Brian Towles, Route packets, net wires: on-chip inteconnectoin networks, Proceedings of the 38th conference on Design automation, p.684-689, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379048]
• 6: E. V. der Tol and E. Jaspers. Mapping of mepg-4 decoding on a flexible architecture platform. In SPIE2002, pages 1--13, Jan. 2002.
• 7: R. E. Gomory and T. C. Hu. Multi-terminal network flows. Journal of Soc. Industrial Appl. Math., 9(4):551--569, Dec. 1961.
• 8: Jingcao Hu , Radu Marculescu, Energy-aware mapping for tile-based NoC architectures under performance constraints, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan [doi>10.1145/1119772.1119818]
• 9: Jingcao Hu , Radu Marculescu, Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures, Proceedings of the conference on Design, Automation and Test in Europe, p.10688, March 03-07, 2003
• 10: E. Jaspers and P. de With. Chip-set for video display of multimedia information. IEEE Transaction on Consumer Electronics, 45(3):707--716, Aug. 1999.
• 11: Srinivasan Murali , Giovanni De Micheli, Bandwidth-Constrained Mapping of Cores onto NoC Architectures, Proceedings of the conference on Design, automation and test in Europe, p.20896, February 16-20, 2004
• 12: J. Plosila, T. Seceleanu, and P. Liljeberg. Implementation of a self-timed segmented bus. IEEE Journals on Design and Test of Computers, 20(6):44--50, 2003.
• 13: Silicore Corporation. WISHBONE System-On-Chip Interconnection Architecture for Portable IP Cores, 2001.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Topology (e.g., bus, point-to-point)

General Terms:
Design

Keywords:
NoC design, application-specific, low-power, networks on chip, systems on chips