An energy efficient TLB design methodology

ABSTRACT

This paper researches Translation Look-aside Buffer (TLB) of embedded processor. Based on an analysis of design-related factors: power, area, critical path and performance of our research model-Godson-I, a low-power TLB design is proposed without sacrifice of performance and timing. Using this method, the following results are achieved: power of TLB-RAM reduces 92.7% and area of TLB-RAM reduces 50%. Compared with other methods, the hit rate of this design is much higher and the accessing conflict to RAM between ITLB and DTLB is much reduced. Although our work targets to Godson-I, the proposed methodology should be applicable to other designs

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Associative memories

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

General Terms:
Design, Experimentation, Performance

Keywords:
Godson-I, TLB, embedded processor design, energy efficient, low-power consumption, single-port RAM