Fast configurable-cache tuning with a unified second-level cache

ABSTRACT

Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or a second level with separate instruction and data configurable caches. We instead use a commercially-common unified second level, a seemingly minor difference that actually expands the configuration space from 500 to about 20,000. We develop additive way tuning for tuning a cache subsystem with this large space, yielding 62% energy savings and 35% performance improvements over a non-configurable cache, greatly outperforming an extension of a previous method

REFERENCES

• 1: Rajeev Balasubramonian , David Albonesi , Alper Buyuktosunoglu , Sandhya Dwarkadas, Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.245-257, December 2000, Monterey, California, United States [doi>10.1145/360128.360153]
• 2: EEMBC, the Embedded Microprocessor Benchmark Consortium, www.eembc.org.
• 3: Givargis, T., Vahid, F. Platune: a tuning framework for system-on-a-chip platforms. IEEE Transactions on Computer Aided Design, November 2002.
• 4: Ann Gordon-Ross , Frank Vahid , Nikil Dutt, Automatic Tuning of Two-Level Caches to Embedded Applications, Proceedings of the conference on Design, automation and test in Europe, p.10208, February 16-20, 2004
• 5: Gordon-Ross, A., Vahid, F., Dutt, N., Fast configurable-cache tuning with a unified second-level cache. UC Riverside Technical Report UCR-CS-2005-05002.
• 6: Afzal Malik , Bill Moyer , Dan Cermak, A low power unified cache architecture providing power and performance flexibility (poster session), Proceedings of the 2000 international symposium on Low power electronics and design, p.241-243, July 25-27, 2000, Rapallo, Italy [doi>10.1145/344166.344610]
• 7: Maurizio Palesi , Tony Givargis, Multi-objective design space exploration using genetic algorithms, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado [doi>10.1145/774789.774804]
• 8: Personal communication with M*CORE designers.
• 9: Reinman, G., Jouppi, N.P. Cacti2.0: an integraded cache timing and power model. COMPAQ Western Research Lab, 1999.
• 10: Sherwood, T., Perelman, E., Hamerly, G., Sair, S., Calder, B. Discovering and Exploiting Program Phases, IEEE Micro: Micro's Top Picks from Computer Architecture Conferences, December 2003.
• 11: Alexander V. Veidenbaum , Weiyu Tang , Rajesh Gupta , Alexandru Nicolau , Xiaomei Ji, Adapting cache line size to application behavior, Proceedings of the 13th international conference on Supercomputing, p.145-154, June 20-25, 1999, Rhodes, Greece [doi>10.1145/305138.305188]
• 12: Chuanjun Zhang , Frank Vahid , Walid Najjar, A highly configurable cache architecture for embedded systems, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California
• 13: Chuanjun Zhang , Frank Vahid , Roman Lysecky, A Self-Tuning Cache Architecture for Embedded Systems, Proceedings of the conference on Design, automation and test in Europe, p.10142, February 16-20, 2004

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

General Terms:
Design

Keywords:
architecture tuning, cache exploration, cache hierarchy, cache optimization, configurable cache, embedded systems, low energy, low power