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Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 2005 international symposium on Low power electronics and design table of contents
San Diego, CA, USA
SESSION: Power management and voltage scaling table of contents
Pages: 287 - 292  
Year of Publication: 2005
ISBN:1-59593-137-6
Authors
Fen Xie  Princeton University, Princeton, NJ
Margaret Martonosi  Princeton University, Princeton, NJ
Sharad Malik  Princeton University, Princeton, NJ
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 4,   Downloads (12 Months): 47,   Citation Count: 8
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ABSTRACT

Dynamic voltage/frequency scaling (DVFS) has been shown to be an efficient power/energy reduction technique. Various runtime DVFS policies have been proposed to utilize runtime DVFS opportunities. However, it is hard to know if runtime DVFS opportunities have been fully exploited by a DVFS policy without knowing the upper bounds of possible energy savings. We propose an exact but exponential algorithm to determine the upper bound of energy savings. The algorithm takes into consideration the switching costs, discrete voltage/frequency voltage levels and different program states. We then show a fast linear time heuristic can provide a very close approximate to this bound


REFERENCES

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CITED BY  8

Collaborative Colleagues:
Fen Xie: colleagues
Margaret Martonosi: colleagues
Sharad Malik: colleagues