Complexity reduction in an nRERL microprocessor

ABSTRACT

We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers required for the phase aligning in the adiabatic microprocessor. Furthermore, by breaking the logic reversibility with self-energy recovery circuits, we also reduced its complexity as well as its energy consumption.We integrated an 8-bit nRERL microprocessor with an 8-phase clocked power generator into a chip with 0.25mm CMOS technology. Its minimum energy consumption of 4.67μA/MHz was measured at Vdd=2.4V and f=651kHz, which was about 40% compared to the previous 6-phase version. Its circuit complexity was also reduced down to 65% that of its 6-phase version.

REFERENCES

• 1: J. Lim, D. -G. Kim, and S. -I. Chae, "nMOS reversible energy recovery logic for ultra-low-energy applications," IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 865--875, Jun. 2000.
• 2: J. Lim, D. -G. Kim, and S. -I. Chae, "A 16-b carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems," IEEE Journal of Solid-State Circuits, vol. 34, no. 6, pp. 898--903, June 1999.
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Microprocessors and microcomputers

General Terms:
Design

Keywords:
buffer skipping, clocked power generator (CPG), complexity reduction, microprocessor, nMOS reversible energy recovery logic (nRERL), reversibility breaking