A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations

ABSTRACT

This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization in nanometer scale designs taking all significant parameter variations into account. The relative effect of different device, interconnect and environmental variations on delay and different components of power has been studied. A probabilistic framework to optimize buffer-interconnect designs under variations has been presented and results are compared with those obtained through simple deterministic optimization. Also, statistical models for delay and power under parameter variations have been developed using linear regression techniques. Under statistical analysis, both power and performance of buffer-interconnect designs are shown to degrade with increasing amount of variations. Also, % error in power estimation for power-optimal repeater designs is shown to be significant if variations are not taken into account. Furthermore, it has been shown that due to variations, significantly higher penalties in delay are needed to operate at power levels similar to those under no variations. Finally, the percentage savings in total power for a given penalty in delay are shown to improve with increasing amount of parameter variations.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

General Terms:
Design, Performance

Keywords:
buffer-interconnect system, parameter variations, sensitivity analysis, statistical delay and power models, statistical optimization