A simple mechanism to adapt leakage-control policies to temperature

ABSTRACT

Leakage power reduction in cache memories continues to be a critical area of research because of the promise of a significant pay-off. Various techniques have been developed so far that can be broadly categorized into state-preserving (e.g., Drowsy Caches) and non-state preserving (e.g., Cache Decay). Decay saves more leakage but also incurs dynamic power overhead in the form of induced misses. Previous work has shown that depending on the leakage vs. dynamic power trade-off, one or the other technique can be better. Several factors such as cache architecture, technology parameters and temperature, affect this trade-off. Our work proposes the first mechanism ---to the best of our knowledg--- that takes into account temperature in adjusting the leakage control policy at run time. At very low temperatures, leakage is relatively weak so the need to tightly control it is not as important as the need to minimize extra dynamic power (e.g., decay-induced misses) or performance loss. We use a hybrid decay+drowsy policy where the main benefit comes from decaying cache lines while the drowsy mode is used to save leakage in long decay intervals. To adapt the decay mode to temperature, we propose a simple triggering mechanism that is based on the principles of decaying 4T thermal sensors and, as such, tied to temperature. The hotter the cache is, the faster cache lines are decayed since it is beneficial to do so with very high leakage currents.Conversely, when the cache temperature is low, our mechanism defers putting cache lines in decay mode to avoid dynamic power overhead but still saves a significant amount of leakage using the drowsy mode. Our study shows that across a wide range of temperatures, the simple adaptability of our proposal yields consistently better results than either the decay mode, or drowsy mode alone, improving over the best by as much as 33%

REFERENCES

• 1: Weidong Liu, et al. "BSIM3v3.2 MOSFET Model User's Manual," Dept. of EE and CS, U.C. Berkeley.
• 2: Krisztián Flautner , Nam Sung Kim , Steve Martin , David Blaauw , Trevor Mudge, Drowsy caches: simple techniques for reducing leakage power, Proceedings of the 29th annual international symposium on Computer architecture, p.148, May 25-29, 2002, Anchorage, Alaska
• 3: Michael Powell , Se-Hyun Yang , Babak Falsafi , Kaushik Roy , T. N. Vijaykumar, Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories, Proceedings of the 2000 international symposium on Low power electronics and design, p.90-95, July 25-27, 2000, Rapallo, Italy [doi>10.1145/344166.344526]
• 4: Stefanos Kaxiras , Zhigang Hu , Margaret Martonosi, Cache decay: exploiting generational behavior to reduce cache leakage power, Proceedings of the 28th annual international symposium on Computer architecture, p.240-251, June 30-July 04, 2001, Göteborg, Sweden
• 5: S. Kaxiras, Polychronis Xekalakis "Decaying 4T Thermal/Leakage Sensors," In Proc. ISLPED, 2004.
• 6: Yan Meng , Timothy Sherwood , Ryan Kastner, On the Limits of Leakage Power Reduction in Caches, Proceedings of the 11th International Symposium on High-Performance Computer Architecture, p.154-165, February 12-16, 2005 [doi>10.1109/HPCA.2005.23]
• 7: Yingmin Li , Dharmesh Parikh , Yan Zhang , Karthik Sankaranarayanan , Mircea Stan , Kevin Skadron, State-Preserving vs. Non-State-Preserving Leakage Control in Caches, Proceedings of the conference on Design, automation and test in Europe, p.10022, February 16-20, 2004
• 8: E. J. McLellan , D. A. Webb, The Alpha 21264 Microprocessor Architecture, Proceedings of the International Conference on Computer Design, p.90, October 05-05, 1998
• 9: Y. Ye, S. Borkar, and V. De, "A Technique for StandbyLeakage Reduction in High-Performance Circuits," Symp.ofVLSI Circuits, pp. 40--41, 1998.
• 10: Trevor Pering , Tom Burd , Robert Brodersen, The simulation and evaluation of dynamic voltage scaling algorithms, Proceedings of the 1998 international symposium on Low power electronics and design, p.76-81, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280790]
• 11: Bhaskar Chatterjee , Manoj Sachdev , Steven Hsu , Ram Krishnamurthy , Shekhar Borkar, Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871538]
• 12: High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness, Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors, p.227, September 17-20, 2000
• 13: Huiyang Zhou , Mark C. Toburen , Eric Rotenberg , Thomas M. Conte, Adaptive Mode Control: A Static-Power-Efficient Cache Design, Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques, p.61, September 08-12, 2001
• 14: S. Velusamy, et al. "Adaptive cache decay using formal feedback control," In Proc. WMPI-2, May 2002.
• 15: Hari Ananthan , Chris H. Kim , Kaushik Roy, Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA [doi>10.1145/1013235.1013244]
• 16: S. Mutah, et al. "1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold Voltage CMOS," IEEE Journal of Solid-State Circuits, 30(8):847--853, 1995.
• 17: Mohab Anis , Mohamed Mahmoud , Mohamed Elmasry , Shawki Areibi, Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514041]
• 18: Liqiong Wei , Zhanping Chen , Mark Johnson , Kaushik Roy , Vivek De, Design and optimization of low voltage high performance dual threshold CMOS circuits, Proceedings of the 35th annual conference on Design automation, p.489-494, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277179]
• 19: Y. Zhang, et al. "Hotleakage: An architectural, temperature-aware model of subthreshold and gate leakage," Tech. Report CS-2003-05, CS Dept., University of Virginia, Mar. 2003.
• 20: J. Adam Butts , Gurindar S. Sohi, A static power model for architects, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.191-201, December 2000, Monterey, California, United States [doi>10.1145/360128.360148]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Adaptable architectures

General Terms:
Design, Performance

Keywords:
cache decay, drowsy cache, hybrid leakage mechanism, thermal adaptation