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Energy-aware fetch mechanism: trace cache and BTB customization
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 2005 international symposium on Low power electronics and design table of contents
San Diego, CA, USA
SESSION: Micro-architectural techniques table of contents
Pages: 42 - 47  
Year of Publication: 2005
ISBN:1-59593-137-6
Authors
Daniel Chaver  Universidad Complutense, Madrid, Spain
Miguel A. Rojas  Universidad Complutense, Madrid, Spain
Luis Pinuel  Universidad Complutense, Madrid, Spain
Manuel Prieto  Universidad Complutense, Madrid, Spain
Francisco Tirado  Universidad Complutense, Madrid, Spain
Michael C. Huang  University of Rochester, Rochester, NY
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 5,   Downloads (12 Months): 16,   Citation Count: 1
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ABSTRACT

A highly-efficient fetch unit is essential not only to obtain good performance but also to achieve energy efficiency. However, existing designs are inflexible and depending on program behavior, can be either insufficient or an overkill. We introduce a phase-based adaptive fetch mechanism that can be dynamically adjusted based on feedback information of the program behavior. This design adds very little hardware complexity and relegates complex tasks to the software components. It is also very effective: saving 26.8% and 34.1% fetch energy on average compared with a conventional and a trace cache-based fetch unit, respectively. At the same time, performance is improved by 5.7% and 0.6%, respectively


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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J. S. Hu, N. Vijaykrishnan, M. J. Irwin, M. Kandemir. Optimizing Power Efficiency in Trace Cache Fetch Unit. Technical Report, Department of Computer Science and Engineering, Pennsylvania State University, 2003.
 
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D. H. Albonesi. Selective Cache Ways: On-Demand Cache Resource Allocation. Journal of Instruction-Level Parallelism, Vol. 2. May, 2000.
 
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M. C. Huang, D. Chaver, L. Pinuel, M. Prieto, and F. Tirado. Customizing the Branch Predictor to Reduce Complexity and Energy Consumption. IEEE Micro 23(5):12--25, September 2003.
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O. J. Santana, A. Ramirez, M. Valero. Reducing Fetch Architecture Complexity Using Procedure Inlining. INTERACT-8, Madrid, Spain. February 2004.
 
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Michele Co and Kevin Skadron. Evaluating the Energy Efficiency of Trace Caches. Technical Report CS-2003-19, University of Virginia, 2003.


Collaborative Colleagues:
Daniel Chaver: colleagues
Miguel A. Rojas: colleagues
Luis Pinuel: colleagues
Manuel Prieto: colleagues
Francisco Tirado: colleagues
Michael C. Huang: colleagues