Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture

ABSTRACT

In recent years, advanced applications that require high processing performance are executed on portable and mobile devices. Those devices require high-performance and low-power processors. To satisfy this requirement, we propose to exploit information regarding instruction criticality. In order to reduce energy consumption with maintaining high performance, each functional units in our processor has different latency and energy consumption. This paper describes the best combination of functional units for the criticality-based low-power processor. The evaluated results show two fast and four slow combination is the best, when the total number of its functional units is six.

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