ACM Home Page
Please provide us with feedback. Feedback
WCRT analysis for a uniprocessor with a unified prioritized cache
Full text PdfPdf (181 KB)
Source ACM SIGPLAN Notices archive
Volume 40 ,  Issue 7  (July 2005) table of contents
Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
SESSION: Caching table of contents
Pages: 175 - 182  
Year of Publication: 2005
ISSN:0362-1340
Also published in ...
Authors
Yudong Tan  Georgia Institute of Technology, Atlanta, GA
Vincent J. Mooney, III  Georgia Institute of Technology, Atlanta, GA
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 17,   Citation Count: 1
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1070891.1065935
What is a DOI?

ABSTRACT

In this paper, we investigate the problem of inter-task cache interference in preemptive multi-tasking real-time systems. A prioritized cache is used to reduce cache conflicts among tasks by partitioning the cache. Cache partitions are assigned to tasks according to their priorities. We extend a known tool, SYMTA, in order to estimate the Worst Case Execution Time of tasks executing on a uniprocessor with a unified prioritized L1 cache. Furthermore, we apply a formal timing analysis approach to estimate the Worst Case Response Time of tasks using the prioritized cache. The prioritized cache is compared to a conventional set associative cache of the same size. Our experiments show that the WCRT estimate can be reduced up to 50% when a prioritized cache is used.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
 
3
D. Kirk. Smart (strategic memory allocation for real-time) cache design. In Proceedings of the Real-Time Systems Symposium, pages 229--237, December 1989.
 
4
 
5
6
 
7
N. Maki, K. Hoson, and A. Ishida. A data-replace-controlled cache memory system and its performance evaluations. In Proceedings of the IEEE Region 10 Conference, pages 471--474, April 1999.
 
8
Mentor Graphics, XRAY® Debugger. http://www.mentor.com/xray/.
 
9
MediaBench, http://cares.icsl.ucla.edu/MediaBench/.
 
10
Mentor Graphics, Hardware/Software Co-Verification: Seamless. Avaliable HTTP: http://www.mentor.com/seamless/.
11
12
13
 
14
G. Suh, L. Rudolph, and S. Devadas. Dynamic cache partitioning for simultaneous multithreading systems. In Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, pages 116--127, September 2001.
 
15
Synopsys, http://www.synopsys.com/products/simulation/simulation.html.
 
16
Y. Tan and V. Mooney. A prioritized cache for multi-tasking real-time systems. In Proceedings of the 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'03), pages 168--175, April 2003.
 
17
 
18
Y. Tan and V. Mooney. Integrate inter- and intra- cache eviction anlaysis for preemptive multi-tasking real-time systems. In Proceedings of the 8th International Workshop on Software and Compilers for Embedded Systems (SCOPES'04), pages 200--206, September 2004.
 
19
 
20
21
22
 
23
 
24
A. Wolfe. Software-based cache partitioning for real-time applications. In Proceedings of the 3rd Workshop on Responsive Computer Systems, September 1993.


Collaborative Colleagues:
Yudong Tan: colleagues
Vincent J. Mooney, III: colleagues