On the design of the local variable cache in a hardware translation-based java virtual machine

ABSTRACT

Hardware bytecode translation is a technique to improve the performance of the Java Virtual Machine (JVM), especially on the portable devices for which dynamic compilation is infeasible. However, since the translation is done on a single bytecode basis, it is likely to generate frequent memory accesses for local variables which can be a performance bottleneck.In this paper, we propose to add a small register file to the datapath of the hardware-translation based JVM and use it as a local variable cache. We evaluate the effectiveness of the local variable cache against the size of the local variable cache which determines the chip area overhead and the operating speed. We also discuss the mechanisms for the efficient parameter passing and the on-the-fly profiling.With two types of exceptions, a 16-entry local variable cache achieved hit ratios of 60 to 98%. The first type of exceptions is represented by the FFT, which accesses more than 16 local variables. In this case, on-the-fly profiling was effective. The hit ratio of 16-entry cache for the FFT was increased from 44 to 83%. The second type of exception is represented by the SAXON XSLT processor for which cold misses were significant. The proposed parameter passing mechanism turned 6.4 to 13.3% of total accesses from miss to hit to the local variable cache.

REFERENCES

• 1: Tim Lindholm , Frank Yellin, Java Virtual Machine Specification, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1999
• 2: Douglas Kramer, "The Java. Platform. A White Paper", JAVASOFT, May 1996.
• 3: "The Java HotSpot. Virtual Machine. Technical White Paper", Sun Microsystems Inc., May 2001.
• 4: Steve Steel, "WHITE PAPER ACCELERATING TO MEET THE CHALLENGE OF EMBEDDED JAVA", ARM Limited, Nov 2001.
• 5: "JSTAR - Java Coprocessor: High Performance, Low Cost, Low Power Java Virtual Machine Accelerator", Nazomi Communications, Inc.
• 6: Ramesh Radhakrishnan , Ravi Bhargava , Lizy K. John, Improving Java performance using hardware translation, Proceedings of the 15th international conference on Supercomputing, p.427-439, June 2001, Sorrento, Italy [doi>10.1145/377792.377901]
• 7: Ashish Sethi and Matt Kubiczek, "Custom processors rev Java execution", http://www.eetimes.com/story/OEG20020329S0016, EE Times, April 2001.
• 8: ORDER GRANTING MOTION FOR PARTIAL SUMMARY JUDGMENT OF NON-INFRINGEMENT, Case No. C 02-02521-JF, UNITED STATES DISTRICT COURT, NORTHERN DISTRICT OF CALIFORNIA, SAN JOSE DIVISION, September 30, 2003.
• 9: D. Gregg, J. Power and J. Waldron, "Benchmarking the Java Virtual Architecture - The SPEC JVM98 Benchmark Suite", Java Microarchitectures, pp1--18, Kluwer Academic.
• 10: Kaffe.org, http://www.kaffe.org.
• 11: "SciMark 2.0 Java Numerical Benchmark", http://math.nist.gov/scimark2/credits.html.
• 12: "SAXON The XSLT and XQuery Processor", http://saxon.sourceforge.net/
• 13: "DataPower: XSLTMark XSLT Performance Benchmark", http://www.datapower.com/xmldev/xsltmark.html
• 14: "JOrbis -- Pure Java Ogg Vorbis Decoder", http://www.jcraft.com/jorbis/, JCraft, Inc.
• 15: "The Embedded CaffeineMark", Pendragon Software Corporation, 1997.
• 16: "The SPARC Architecture Manual", Version 9, SPARC International, September 2000.
• 17: "SPARC-V8 Supplement, SPARC-V8 Embedded (V8E) Architecture Specification", Version 1.0, SPARC International, October 23, 1996.
• 18: "picoJava-II Processor Core", Sun Microsystems, April 1999.
• 19: John Glossner and Stamatis Vassiliadis, "Delft-Java Dynamic Translation", in Proc. of 25th Euromicro Conference, Vol. 1, pp 1057--1062, Sep. 1999.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES

General Terms:
Design, Performance

Keywords:
hardware-translation, java virtual machine, memory hierarchy