A code compression advisory tool for embedded processors

ABSTRACT

We present a tool which is designed to be used as a code compression advisory system for object code to be run on an embedded processor. All the compression schemes support run-time random decompression. Given the machine instruction set architecture, the encoding of instructions, and a set of object programs to be compressed, the tool analyzes the code, gathers statistics about static instruction frequencies and other relevant information, and performs a relative evaluation of a suite of compression strategies. The tool produces as output, the sizes of the compressed code, the Line Address Table (if one is required), and the dictionary (if there is only one) or the sizes of all dictionaries if there are several, for various choices of parameters input by the user. The final result helps one to decide a code compression strategy for the input processor. We have used the tool to evaluate alternate schemes for a suite of benchmarks for the TI TMS320C62x instruction set architecture and the Intel StrongARM processor and report results.

REFERENCES

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INDEX TERMS

Primary Classification:
  E. Data
  E.4 CODING AND INFORMATION THEORY

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.1 Single Data Stream Architectures
          Subjects: RISC/CISC, VLIW architectures

General Terms:
Design, Performance

Keywords:
code compression, embedded system tool, run time decompression