MiniBit: bit-width optimization via affine arithmetic

ABSTRACT

MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static analysis via affine arithmetic. We describe methods to minimize both the integer and fraction parts of fixed-point signals with the aim of minimizing circuit area. Our range analysis technique identifies the number of integer bits required. For precision analysis, we employ a semi-analytical approach with analytical error models in conjunction with adaptive simulated annealing to find the optimum number of fraction bits. Improvements for a given design reduce area and latency by up to 20% and 12% respectively, over optimum uniform fraction bit-widths on a Xilinx Virtex-4 FPGA.

REFERENCES

• 1: Altaf Abdul Gaffar , Oskar Mencer , Wayne Luk , Peter Y. K. Cheung, Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs, Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.79-88, April 20-23, 2004
• 2: R. Cmar , L. Rijnders , P. Schaumont , S. Vernalde , I. Bolsens, A methodology and design environment for DSP ASIC fixed point refinement, Proceedings of the conference on Design, automation and test in Europe, p.56-es, January 1999, Munich, Germany [doi>10.1145/307418.307503]
• 3: Claire F. Fang , Rob A. Rutenbar , Tsuhan Chen, Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.275, November 09-13, 2003 [doi>10.1109/ICCAD.2003.68]
• 4: Claire Fang Fang , Rob A. Rutenbar , Markus Püschel , Tsuhan Chen, Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775960]
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Automatic synthesis

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Optimization

General Terms:
Algorithms, Design, Experimentation, Performance

Keywords:
FPGA, affine arithmetic, annealing, bit-width, fixed-point, simulated