Power emulation: a new paradigm for power estimation

ABSTRACT

In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the observation that most power estimation tools typically perform the following sequence of operations: simulating the circuit to obtain value traces or statistics for the inputs of its constituent components, evaluating power models for each circuit component based on the input values seen during simulation, and aggregating the power consumption of individual components to compute the circuit's power consumption. We further recognize that the steps involved in power estimation (power model evaluation, aggregation) can themselves be thought of as synthesizable functions and implemented as hardware circuits. Thus, any given design can be enhanced by adding to it .power estimation hardware., and the resulting power model enhanced circuit can be mapped onto a hardware prototyping platform. While drastic speedups in power estimation (orders of magnitude) are possible using this approach, a significant challenge arises due to the increase in circuit size as a result of adding power estimation hardware. We propose a systematic methodology to reduce the size of the power model enhanced circuit through a suite of techniques, including power model reuse across different circuit components, regulating the granularity of components for power modeling, exploiting inter-component power correlations, resource sharing for power model computations, and the use of block memories for efficient storage within power models. We demonstrate the benefits of the proposed power emulation paradigm by applying it to register-transfer level (RTL) power estimation for industrial designs, resulting in speedups from around 10X to over 500X compared to state-of-the-art commercial power estimation tools.

REFERENCES

• 1: "International Technology Roadmap for Semiconductors, 2001 Edition." http://public.itrs.net/Files/2001ITRS/Home.htm.
• 2: "Galaxy Power Products, Synopsys Inc. (http://www.synopsys.com).".
• 3: "PowerTheater, Sequence Design Inc. (http://www.sequencedesign.com).".
• 4: "PowerChecker, BullDAST s.r.l. (http://www.bulldast.com).".
• 5: "ORINOCO, ChipVision Design Systems. (http://www.chipvision.com).".
• 6: Srivaths Ravi , Anand Raghunathan , Srimat Chakradhar, Efficient RTL Power Estimation for Large Designs, Proceedings of the 16th International Conference on VLSI Design, p.431, January 04-08, 2003
• 7: Massoud Pedram , Jan M. Rabaey, Power Aware Design Methodologies, Kluwer Academic Publishers, Norwell, MA, 2002
• 8: Enrico Macii , Massoud Pedram , Fabio Somenzi, High-level power modeling, estimation, and optimization, Proceedings of the 34th annual conference on Design automation, p.504-511, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266268]
• 9: Anand Raghunathan , Niraj K. Jha , Sujit Dey, High-Level Power Analysis and Optimization, Kluwer Academic Publishers, Norwell, MA, 1998
• 10: Diana Marculescu , Radu Marculescu , Massoud Pedram, Information theoretic measures of energy consumption at register transfer level, Proceedings of the 1995 international symposium on Low power design, p.81-86, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224096]
• 11: M. Nemani and F. Najm, "High-level area and power estimation for VLSI circuits," IEEE Trans. Computer-Aided Design, vol. 18, pp. 697--713, June 1999.
• 12: Paul E. Landman , Jan M. Rabaey, Architectural power analysis: the dual bit type method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.2, p.173-187, June 1995 [doi>10.1109/92.386219]
• 13: L. Benini, A. Bogliolo, M. Favalli, and G. De Micheli, "Regression models for behavioral power estimation," in Proc. Int. Wkshp. Power & Timing Modeling, Optimization, and Simulation, 1996.
• 14: Qing Wu , Qinru Qiu , Massoud Pedram , Chih-Shun Ding, Cycle-accurate macro-models for RT-level power analysis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.6 n.4, p.520-528, Dec. 1998 [doi>10.1109/92.736123]
• 15: Rafael Peset Llopis , Kees Goossens, The petrol approach to high-level power estimation, Proceedings of the 1998 international symposium on Low power electronics and design, p.130-132, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280830]
• 16: R. Mehra and J. Rabaey, "Behavioral level power estimation and exploration," in Proc. Int. Wkshp. Low Power Design, pp. 197--202, Apr. 1994.
• 17: F. Ferrandi , F. Fummi , E. Macii , M. Poncino , D. Sciuto, Power estimation of behavioral descriptions, Proceedings of the conference on Design, automation and test in Europe, p.762-766, February 23-26, 1998, Le Palais des Congrés de Paris, France
• 18: Lars Kruse , Eike Schmidt , Gerd Jochens , Ansgar Stammermann , Arne Schulz , Enrico Macii , Wolfgang Nebel, Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.1, p.3-15, Feb. 2001 [doi>10.1109/92.920813]
• 19: Vivek Tiwari , Sharad Malik , Andrew Wolfe, Power analysis of embedded software: a first step towards software power minimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.437-445, Dec. 1994 [doi>10.1109/92.335012]
• 20: Milind B. Kamble , Kanad Ghose, Analytical energy dissipation models for low-power caches, Proceedings of the 1997 international symposium on Low power electronics and design, p.143-148, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263310]
• 21: Mauro Chinosi , Roberto Zafalon , Carlo Guardiani, Automatic characterization and modeling of power consumption in static RAMs, Proceedings of the 1998 international symposium on Low power electronics and design, p.112-114, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280815]
• 22: Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.4, p.500-508, Aug. 2001 [doi>10.1109/92.931227]
• 23: Kanishka Lahiri , Anand Raghunathan, Power Analysis of System-Level On-Chip Communication Architectures, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'04), p.236-241, September 08-10, 2004 [doi>10.1109/CODES+ISSS.2004.47]
• 24: R. Burch, F. N. Najm, P. Yang, and T. Trick, "A Monte Carlo approach for power estimation," IEEE Trans. VLSI Systems, vol. 1, pp. 63--71, Mar. 1993.
• 25: Mauro Chinosi , Roberto Zafalon , Carlo Guardiani, Parallel mixed-level power simulation based on spatio-temporal circuit partitioning, Proceedings of the 36th ACM/IEEE conference on Design automation, p.562-567, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309998]
• 26: Joel Coburn , Srivaths Ravi , Anand Raghunathan, Hardware Accelerated Power Estimation, Proceedings of the conference on Design, Automation and Test in Europe, p.528-529, March 07-11, 2005 [doi>10.1109/DATE.2005.168]
• 27: "Synplify Pro, Synplicity Inc. (http://www.synplicity.com).".
• 28: "Virtex-II FPGA and tools, Xilinx Inc. (http://www.xilinx.com).".
• 29: G. G. Roussas, A Course in Mathematical Statistics, Second Edition. Academic Press, London, UK, 1997.
• 30: Anil K. Jain , Richard C. Dubes, Algorithms for clustering data, Prentice-Hall, Inc., Upper Saddle River, NJ, 1988
• 31: "Using AMPL/MINOS (http://www.ampl.com/BOOKLETS/ampl-minos.pdf).".
• 32: B. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs," The Bell System Tech J., vol. 49, pp. 291--307, Feb. 1970.
• 33: K. Wakabayashi, C-Based High-Level Synthesis System, "CYBER"-Design Experience-, vol. 41, pp. 264--268. July 2000.
• 34: CB130 Family 0.13um CMOS CBIC http://www.necel.com/cbic/en/cb130/cb130.html.NEC Electronics, Inc., Sept. 2000.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Simulation

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Modeling techniques

General Terms:
Algorithms, Design, Experimentation, Measurement, Performance

Keywords:
FPGA, design, design methodologies, emulation, hardware acceleration, macromodels, power estimation, register-transfer level, simulation